Denon-AVR2802-av-sm维修电路原理图.pdf

Hi-Fi Component SERVICE MANUAL MODEL AVR-2802/982 AV SURROUND RECEIVER ? Some illustrations using in this service manual are slightly different from the actual set. For U.S.A., Canada, Europe, Asia, China, Hong Kong Edge detection is “Ed”; Detection by both shifting is “E Serial data detection is “S” (Serial data output is also “S”). Res:State at reset. “H”= Outputs High Level at reset “L”= Outputs Low Level at reset “Z”= Becomes High impedance mode at reset Ini:Initial output state. Function:Function and logical level explanation of signals to be interface. TMP93CS40F (AU: IC301) NameFunction TMP93CS40F Terminal Function Pin No. 1V REFLA/D ref. GND 2A VssA/D GND 3A VccAD +5V 4_NMIINot used (fixed to H) 5P70/TI0C15OCEdLLFixed to L (DSP ROM address cont. out bit 15, not used) 6P71/TO1C16OCEdLLDSP program ROM address cont. out bit 16 7P72/TO2C17OCEdLLDSP program ROM address cont. out bit 17 8P73/TO3ROM/RAMOCEdLLROM/RAM switching control terminal (L:ROM) 9P80/INT4/TI4_INTREQ OUTI/OCEuE&LZDSP request input and cont. output (L:Rq & cont.) 10P81/INT5/TI5B.DOWNIEuE&LZPower down detect (H: Detected) 11P82/TO4OCLL 12P83/TO5_REQOCEuHL MAIN-SUB CPU comm. control output (L: Comm. request from sub) 13P84/INT6/TI6_ACKIEuE&LMAIN-SUB CPU comm. control input (L: Ack. return from main) 14P85/INT7/TI7ERRIE&LDIR control input terminal (LC89055Q)( H: ERR) 15P86/TO6ILvZ(GND) 16P97/INT0_CSIEdE&L DIR control input terminal (LC89055Q), when CH status change LH 17P90/TXD0SIOCMAIN-SUB CPU comm. control terminal (data output) 18P91/RXD0SOIMAIN-SUB CPU comm. control terminal (data input) 19P92/_CTS0/SCLK0CLKI/OCMAIN-SUB CPU comm. control terminal (I2C clock in/output) 20P93/TXD1OCZL 21P94/RXD1OCZL 22P95/SCLK1OCZL 23AM8/_16Fixed to +5V 24CLKOCEu 25Vcc+5V 26VssI/O1GND 27X1XinIXtal connection 28X2XoutOXtal connection 29_EAFixed to +5V 30_RESETRESET2_IEuLvLReset input (controlled by main CPU) 31P96/XT1A/D RESETONEuHHA/D control terminal (L: Reset) 32P97/XT2OCEdLL 33TEST1IConnected to TEST2 34TEST2IConnected to TEST1 35PA0DINAOCEdLLDigital input switching control output 36PA1DINBOCEdLLDigital input switching control output 37PA2OCLL 38PA3DINCOCEdLLDigital input switching control output 39PA4DOUTAOCEdLLDigital output switching control output 40PA5DOUTBOCEdLLDigital output switching control output SymbolI/OTypeOpDetResInit NameFunction Pin No. 41PA6DEEMPOCEdLLDAC de-emphasis filter cont. out terminal (H:ON) 42PA7/SCOUT96k-DACOCLLDAC control terminal (H: Sample frequency 96kHz) 43ALEOCLL(Address latch enable) 44Vcc+5V 45P00/AD0(AD0)I/OCZL(EPROM data in D0 / address out A0) 46P01/AD1(AD1)I/OCZL(EPROM data in D1 / address out A1) 47P02/AD2(AD2)I/OCZL(EPROM data in D2 / address out A2) 48P03/AD3(AD3)I/OCZL(EPROM data in D3 / address out A3) 49P04/AD4(AD4)I/OCZL(EPROM data in D4 / address out A4) 50P05/AD5(AD5)I/OCZL(EPROM data in D5 / address out A5) 51P06/AD6(AD6)I/OCZL(EPROM data in D6 / address out A6) 52P07/AD7(AD7)I/OCZL(EPROM data in D7 / address out A7) 53P10/AD8/A8(A8)OCZL(EPROM address out A8) 54P11/AD9/A9(A9)OCZL(EPROM address out A9) 55P12/AD10/A10(A10)OCZL(EPROM address out A10) 56P13/AD11/A11(A11)OCZL(EPROM address out A11) 57P14/AD12/A12(A12)OCZL(EPROM address out A12) 58P15/AD13/A13(A13)OCZL(EPROM address out A13) 59P16/AD14/A14(A14)OCZL(EPROM address out A14) 60P17/AD15/A15(A15)OCZL(EPROM address out A15) 61_WDTOUTOCZHWatch dog output 62VssGND 63Vcc+5V 64P20/A0/A16(A16)OCZL(EPROM address out A16) 65P21/A1/A17DIR CLKOCZLDIR control terminal (LC89055Q) control clock output 66P22/A2/A18DIR CEOCZLDIR control terminal (LC89055Q) control chip enable output 67P23/A3/A19DIR MOSIOCZLDIR control terminal (LC89055Q) control data output 68P24/A4/A20DIR MOSOILvDIR control terminal (LC89055Q) control data input 69P25/A5/A21FGAINOCEdLLFRONT ch GAIN switching control output (H: SW=NO) 70P26/A6/A22DAC-RESETOCEdLHDAC control terminal (L: Power down mode, (rising edge) Reset) 71P27/A7/A23SEL CKOCZLADC/DIR data clock switching control terminal (L: ADC) 72P30/_RD(_RD)OCZL(Flash memory control terminal) 73P31/_WR(_WR)OCZL(Flash memory control terminal) 74P32/_HWRCSIILvDIR control input terminal (L: PCM) 75P33/_WAITERR MUTE_OCEdLLPop noise preventive mute control output (L: Mute) 76P34/_BUSRQILvZGND 77P35/_BUSRQDIG.(AC3) MUTEOCEdZLDigital mute control output (L: AC-3 or DTS decode enable) 78P36/_R/WILvZGND 79P37/_RASDIR RESETOCZLDIR control output (LC89055Q) (L: Reset) 80P40/_CS0/_CAS0OCZL 81P41/_CS1/_CAS1OCZL 82P42/_CS2/_CAS2(_CS0)OCZL(Flash memory control terminal) 83P60/PG00DSP. RESETOCZLDSP reset output terminal (L:Reset) 84P61/PG01I/02 SCD OUTICLvZDSP status data input terminal 85P62/PG02I/03 DSP. CSOZLDSP chip select cont.output (L:Data out) 86P63/PG03I/04 DSP. CLKOCZLDSP data clock output terminal 87P64/PG10I/05 SCD INOCZLDSP data output terminal 88P65/PG11I/06 4527_CEOCZLAD control terminal (AK4527), Chip enable output 89P66/PG12I/07 4527_CLKOCZLAD control terminal (AK4527), Data clock output 90P67/PG13I/08 4527_DINOCZLAD control terminal (AK4527), Data output 91VssGND 92P50/AN0INTTREQ INIEuLvZ 93P51/AN1IEuLvZ 94P52/AN2EMPILvH: EMP on 95P53/AN396K DETILv96k signal detect input, H: 96k 96P54/AN4IEuLvZ 97P55/AN5IEuLvZ 98P56/AN6ACC ON/OFFIEuLvZ 99P57/AN7IEuLvZ 100V REFHAD ref. +5V SymbolI/OTypeOpDetResInit? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 16 AVR-2802/982 AVR-2802/982 17 1,12,23VD1,2,3Digital power supply (+) 2,13,24DGND1,2,3Digital GND 3AUDATA3, XMT958SPDIF transmitter output, Digital audio output 3 4WR, DS, EMWR, GPIO10 Host write strobe, Host data strobe, External memory write enable, General purpose in/output 10 5RD, R/W, EMOE,GPIO11 Host parallel output enable, Host parallel R/W, External memory write enable, General purpose in/output 11 6A1,SCDINHost address bit 1, SPI serial control data input 7A0,SCCLKHost address bit 0, Serial control port clock 8DATA7, EMAD7, GPIO7Bidirectional data bus 7, External memory address 7, General purpose in/output 7 9DATA6, EMAD6, GPIO6Bidirectional data bus 6, External memory address 6, General purpose in/output 6 10DATA5, EMAD5, GPIO5Bidirectional data bus 5, External memory address 5, General purpose in/output 5 11DATA4, EMAD4, GPIO4Bidirectional data bus 4, External memory address 4, General purpose in/output 4 14DATA3, EMAD3, GPIO3Bidirectional data bus 3, External memory address 3, General purpose in/output 3 15DATA2, EMAD2, GPIO2Bidirectional data bus 2, External memory address 2, General purpose in/output 2 16DATA1, EMAD1, GPIO1Bidirectional data bus 1, External memory address 1, General purpose in/output 1 17DATA0, EMAD0, GPIO0Bidirectional data bus 0, External memory address 0, General purpose in/output 0 18CSHost parallel chip select, Host serial SPI chip select 19SCDIO, SCDOUT, PSEL,GPIO9Serial control port data in/output, Parallel port type select, General purpose in/output 9 20INTREQ, ABOOTControl port interrupt request, Automatic boot enable 21EXTMEM, GPIO8External memory chip select, General purpose in/output 8 22SDATAN1PCM audio data input 1 25SCLKN1, STCCLK2PCM audio input bit clock 26LRCLKN1PCM audio input sample rate clock 27CMPDAT, SDATAN2PCM audio data input 2 28CMPCLK, SCLKN2PCM audio input bit clock 29CMPREQ, LRCLKN2PCM audio input sample rate clock 30CLKINMaster clock input 31CLKSELDSP clock select 32FILT2PLL filter 33FILT1PLL filter 34VAAnalog power supply (+) 35AGNDAnalog GND 36RESETMaster reset input 37DDReserved 38DCReserved 39AUDATA2Digital audio output 2 40AUDATA1Digital audio output 1 41AUDATA0Digital audio output 0 42LRCLKAudio output sample rate clock 43SCLKAudio output bit clock 44MCLKAudio master clock A0, SCCLK7 DATA7, EMAD7, GPIO78 DATA6, EMAD6, GPIO69 DATA5, EMAD5, GPIO510 DATA4, EMAD4, GPIO411 VD212 DGND213 DATA3, EMAD3, GPIO314 DATA2, EMAD2, GPIO215 DATA1, EMAD1, GPIO116 DATA0, EMAD0, GPIO0 AUDATA2 DC DD RESET AGND VA FILT1 FILT2 CLKSEL CLKIN CMPREQ, LRCLKN217 CS18 SCDIO, SCDOUT,PSEL, GPIO919 ABOOT, INTREQ20 EXTMEM, GPIO821 SDATAN122 VD323 DGND324 SCLKN1, STCCLK225 LRCLKN126 CMPDAT,SDATAN2, RCV95827 CMPCLK, SCLKN228 39 38 37 36 35 34 33 32 31 30 29 A1, SCDIN RD, R/W, EMOE, GPIO11 WR/DS/EMWR, GPIO10 AUDATA3, XMT958 DGND1 VD1 MCLK SCLK LRCLK AUDATA0 AUDATA1 6 5 4 3 2 1 44 43 42 41 40 Top View CS493292-CL (AU: IC814) ? CS493292-CL Terminal Funtion Port NameFunctionPin No. 18 AVR-2802/982 LC89055W (AU: IC800) Pin NameFunction LC89055W Terminal Function Pin No. 1DISELIData input terminal (select input pin of DIN0, DIN1) 2DOUTOInput bi-phase data through output terminal 3DIN0IAmp built-in coaxial/optical input correspond data input terminal 4DIN1IAmp built-in coaxial/optical input correspond data input terminal 5DIN2IOptical input correspond data input terminal 6DGNDDigital GND 7DVDDDigital power supply 8RIVCO gain control input terminal 9VINIVCO free-run frequency setting input terminal 10LPFOPLL loop filter setting terminal 11AVDDAnalog power supply 12AGNDAnalog GND 13CKOUTOClock output terminal (256fs, 384fs, 512fs, Xtal osc., VCO free-run osc.) 14BCKO64fs clock output terminal 15LRCKOfs clock output terminal (L: Rch, H: Lch, I2S: Reverse) 16DATAOOData output terminal 17XSTATEOInput data detecting result output terminal 18DGNDDigital GND 19DVDDDigital power supply 20XMCKOXtal osc. clock output terminal (24.576MHz or 12.288MHz) 21XOUTOXtal osc. connection output terminal 22XINIXtal osc. connection input terminal, external signal input possible (24.576MHz or 12.288MHz) 23EMPHAOEmphasis information output terminal of channel status 24AUDIOOBit1 output terminal of channel status 25CSFLAGOTop 40bit revise flag output terminal of channel status 26F0/P0/C0OInput fs cal. sig. out / data type out / input word inf. output terminal 27F1/P1/C1OInput fs cal. sig. out / data type out / input word inf. output terminal 28F2/P2/C2OInput fs cal. sig. out / data type out / input word inf. output terminal 29VF/P3/C3OValidity flag out / data type out / input word inf. output terminal 30DVDDDigital power supply 31DGNDDigital GND 32AUTOONon PCM burst data transfer detect sig. output terminal 33BPSYNCONon PCM burst data preamble Pa, Pb, Pc, Pd sync sig. output terminal 34ERROROPLL lock error, data error flag output terminal 35DOOCPU I/F read data output terminal 36DIICPU I/F write data input terminal 37CEICPU I/F chip enable input terminal 38CLICPU I/F clock input terminal 39XSELIFrequency select input pin of XIN Xtal osc. (24.576MHz or 12.288MHz) 40MODE0IMode setting input terminal 41MODE1IMode setting input terminal 42DGNDDigital GND 43DVDDDigital power supply 44DOSEL0IData output format select input terminal 45DOSEL1IData output format select input terminal 46CKSEL0IOutput clock select input terminal 47CKSEL1IOutput clock select input terminal 48XMODEIReset input terminal I/O * For latch-up countermeasure, set digital (DVDD) and analog (AVDD) power on/off in the same timing. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 19 AVR-2802/982 M35015-210SP Terminal Function Pin No.SymbolNameI/OFunction 1OSC1Osc. circuit ext.IExternal terminal for indication oscillator circuit. Standard OSC. freq. is approx. 7MHz. 2OSC2terminal.OWith this OSC. freq., decides horizontal indicatin and character width. 3CSChip select inputI Chip select terminal and turns to “L” when transfer serial data. Hysteresis input. Pull up resistor is built-in. 4SCKSerial clock inputI Takes in serial data of SIN at SCK rise when CS terminal is in “L”. Hysteresis input. Pull up rersist is built-in. 5SINSerial data inputI Serial input of register for indication control and data, and address for indication data memory. Hysteresis input. Pull up rersistor is built-in. 6ACAuto-clear inputI Resets internal circuit of IC at “L” mode. Hysteresi input. Pull up resistor is built-in. 7VDD2Power supply?Power supply terminal of analog system. Connect to +5V. 8CVIDEO Combined video output O Output terminal of combined video signal. Outputs 2Vp-p combined signal. Character output, etc. Overlap CVIN signal and outputs at superimpose. 9LECHA Character level input I Input terminal deciding character output level in combined video signal. color of character is white. 10CVIN Combined video input I Input terminal of external combined video signal. Character output etc. overlap this external combined video signal. 11VssGround?Ground terminal. Connect to GND. 12P0Output port p0O General output or character background signal BL NK1* output is switchable. Polarity can be selected at ROM mask. 13P1Output port P1O General output or character background signal CO1* output is switchable. Polarity can be selected at ROM mask. 14P2Output port P2O General output or character background signal BLNK2* output is switchable. Polarity can be selected at ROM mask. 15P3Output port P3O General output or character background signal CO2* output is switchable. Polarity can be selected at ROM mask. 16OSCOUTOTerminal for external use of sync signal OSC. circuit. Use the freq.: 14.32MHz at NTSC 17OSCINIsystem, 17.73MHz at PAL. system, 14.30MHz at MPAL system. 18HOR* Horizontal sync signal I Inputs horizontal sync signal. Hysteresis input. 19VERT* Vertical sync signal ?Input vertical sync signal. Hysteresis input. Polarity can be selected at ROM mask. 20VDD1Power supplyIPower supply terminal of digital system. Connect to +5V. Ext. terminal for sync sig. OSC. Circuit M35015-210SP (AU: IC453) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ! ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? # ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? $ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ! ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? AVR-2802/982 20 AK4527BVQ (AU:IC602) AK4527BVQ Terminal Function 1 2 3 4 5 6 7