Denon-AVRS500BT-avr-sm维修电路原理图.pdf

MODELJPE3E2EKEAE1E1CE1K AVR-S500BTPP AVR-X510BTPP AV SURROUND RECEIVER Ver. 3 Please use this service manual with referring to the operating instructions without fail. Some illustrations using in this service manual are slightly different from the actual set. For purposes of improvement, specifications and design are subject to change without notice. Please refer to the MODIFICATION NOTICE.e SERVICE MANUAL e D supports TMDS logic level. 48 TXC+ HDMI Output Differential Clock Output. Differential clock output at the TMDS clock rate; supports TMDS logic level. 88 ADV7623 Hardware Manual Rev. 0 March 2010 19 Confidential NDA required Location Mnemonic Type Description 49 TXGND Ground TXAVDD Ground 50 TX0- HDMI Output Differential Output Channel 0 Complement. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 51 TX0+ HDMI Output Differential Output Channel 0 True. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 52 TXGND Ground TXAVDD Ground 53 TX1- HDMI Output Differential Output Channel 1 Complement. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 54 TX1+ HDMI Output Differential Output Channel 1 True. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 55 TXAVDD Power 1.8V power supply for TMDS outputs 56 TX2- HDMI Output Differential Output Channel 2 Complement. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 57 TX2+ HDMI Output Differential Output Channel 2 True. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 58 TXGND Ground TXAVDD Ground 59 CEC Digital I/O Consumer electronic control channel. 60 DGND Ground Ground for DVDD 61 DVDD Power Digital supply voltage (1.8 V) 62 ALSB Digital Input This pin is used to set I2C address of the Rx IO and the Tx Main Map. 63 CSB Digital Input Chip Select pin. This pin must be set low or left floating for the chip to process I2C messages that are destined to the ADV7623. The ADV7623 ignores I2C messages which he receives if this pin is high. 64 EP_SCK Digital Output SPI clock interface for the EDID/OSD 65 EP_CS Digital Output SPI chip selected interface for the EDID/OSD 66 EP_MOSI Digital Output SPI master out/slave in for the EDID/OSD 67 EP_MISO Digital Input SPI master in/slave out for the EDID/OSD 89 ADV7623 Hardware Manual Rev. 0 March 2010 20 Confidential NDA required Location Mnemonic Type Description 68 MCLK_IN Digital Input Audio Reference Clock. 128 N fs with N = 1, 2, 3, or 4. Set to 128 sampling frequency (fs), 256 fs, 384 fs, or 512 fs. Supports 1.8 V to 3.3 V CMOS logic levels. 69 SCLK_IN Digital Input I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V. 70 AP5_IN Digital Input Audio Input Port 5. CMOS logic levels from 1.8 V to 3.3 V. 71 AP4_IN Digital Input Audio Input Port 4. CMOS logic levels from 1.8 V to 3.3 V. 72 DGNDIO Ground Ground for DVDDIO 73 DVDDIO Power Digital I/O supply voltage (3.3 V) 74 AP3_IN Digital Input Audio Input Port 3. CMOS logic levels from 1.8 V to 3.3 V. 75 AP2_IN Digital Input Audio Input Port 2. CMOS logic levels from 1.8 V to 3.3 V. 76 AP1_IN Digital Input Audio Input Port 1. CMOS logic levels from 1.8 V to 3.3 V. 77 AP0_IN Digital Input Audio Input Port 0. CMOS logic levels from 1.8 V to 3.3 V. 78 SDATA Digital I/O I2C port serial data input/output pin. SDA is the data line for the control port. 79 SCL Digital Input I2C port serial clock input. SCL is the clock line for the control port. 80 DGND Ground Ground for DVDD 81 DVDD Power Digital supply voltage (1.8 V) 82 INT1 (AMUTE1) Digital Output Interrupt pin, can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user control. This pin can also output an audio mute signal 83 INT2 (AMUTE2) Digital Output Interrupt pin, can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user control. This pin can also output an audio mute signal. I2C LSB selection. 84 INT_TX Digital Output Interrupt. Open drain. A 2 k pull-up resistor to the microcontroller I/O supply is recommended. 85 DGNDIO Ground Ground for DVDDIO 86 DVDDIO Power Digital I/O supply voltage (3.3 V) 90 ADV7623 Hardware Manual Rev. 0 March 2010 21 Confidential NDA required Location Mnemonic Type Description 87 AP0_OUT Digital Output Audio output port 0. 88 AP1_OUT Digital Output Audio output port 1. 89 AP2_OUT Digital Output Audio output port 2. 90 AP3_OUT Digital Output Audio output port 3. 91 AP4_OUT Digital Output Audio output port 4. 92 DGND Ground Ground for DVDD 93 DVDD Power Digital supply voltage (1.8 V) 94 AP5_OUT Digital Output Audio output port 5. 95 SCLK_OUT Digital Output Audio serial clock output. 96 MCLK_OUT Digital Output Audio master clock output. 97 RESETB Digital Input System reset input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7623 circuitry. 98 PWRDNB Digital Input Active low power-down pin. This pin should be used as a system power detect when the internal EDID is powered from the 5V signal from the HDMI port when connected to active equipment. Pin pulled down internally. 99 PGND Ground Ground for PVDD 100 PVDD Power PLL supply voltage 101 XTAL Miscellaneous Analog Input pin for 28.63636 MHz crystal or an external 1.8 V 28.63636 MHz clock oscillator source to clock the ADV7623. The following crystal frequencies are also supported: 24.576 MHz and 27 MHz. 102 XTAL1 Miscellaneous Analog Crystal output pin. This pin should be left floating if a clock oscillator is used. 103 PVDD Power PLL supply voltage 104 PGND Ground PVDD Ground 105 HP_CTRLA Digital Output Hot Plug Detect for port A. 106 5V_DETA Digital Input 5 V detect pin for port A in the HDMI interface. 107 RTERM Miscellaneous Analog Sets internal termination resistance. A 500 resistor between this pin and GND should be used. 108 DDCA_SDA Digital I/O HDCP slave serial data port A. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant. 109 DDCA_SCL Digital Input HDCP slave serial clock port A. DDCD_SCL is a 3.3 V input that is 5 V tolerant. 110 CVDD Power Receiver comparator supply voltage (1.8V) 91 ADV7623 Hardware Manual Rev. 0 March 2010 22 Confidential NDA required Location Mnemonic Type Description 111 CGND Ground TVDD and CVDD Ground 112 RXA_C- HDMI Input Digital input clock Complement of port A in the HDMI interface. 113 RXA_C+ HDMI Input Digital input clock True of port A in the HDMI interface. 114 TVDD Power Receiver terminator supply voltage (3.3 V) 115 RXA_0- HDMI Input Digital input channel 0 complement of port A in the HDMI interface. 116 RXA_0+ HDMI Input Digital input channel 0 true of port A in the HDMI interface. 117 CGND Ground TVDD and CVDD Ground 118 RXA_1- HDMI Input Digital input channel 1 complement of port A in the HDMI interface. 119 RXA_1+ HDMI Input Digital input channel 1 true of port A in the HDMI interface. 120 TVDD Power Receiver terminator supply voltage (3.3 V) 121 RXA_2- HDMI Input Digital input channel 2 complement of port A in the HDMI interface. 122 RXA_2+ HDMI Input Digital input channel 2 true of port A in the HDMI interface. 123 HP_CTRLB Digital Output Hot Plug Detect for port B. 124 5V_DETB Digital Input 5 V detect pin for port B in the HDMI interface. 125 DGND Ground Ground for DVDD 126 DVDD Power Digital supply voltage (1.8 V) 127 DDCB_SDA Digital I/O HDCP slave serial data ports B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant. 128 DDCB_SCL Digital Input HDCP slave serial clock port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. 129 CVDD Power Receiver comparator supply voltage (1.8V) 130 CGND Ground TVDD and CVDD Ground 131 RXB_C- HDMI Input Digital input clock complement of port B in the HDMI interface. 132 RXB_C+ HDMI Input Digital input clock true of port B in the HDMI interface. 133 TVDD Power Receiver terminator supply voltage (3.3 V) 134 RXB_0- HDMI Input Digital input channel 0 complement of port B in the HDMI interface. 135 RXB_0+ HDMI Input Digital input channel 0 true of port B in the HDMI interface. 136 CGND Ground TVDD and CVDD Ground 137 RXB_1- HDMI Input Digital input channel 1 complement of port 92 MX25L3206EM2I-12G (DIGITAL : IC722) ADV7623 Hardware Manual Rev. 0 March 2010 23 Confidential NDA required Location Mnemonic Type Description B in the HDMI interface. 138 RXB_1+ HDMI Input Digital input channel 1 true of port B in the HDMI interface. 139 TVDD Power Receiver terminator supply voltage (3.3 V) 140 RXB_2- HDMI Input Digital input channel 2 complement of port B in the HDMI interface. 141 RXB_2+ HDMI Input Digital input channel 2 true of port B in the HDMI interface. 142 HP_CTRLC Digital Output Hot Plug Detect for port C. 143 5V_DETC Digital Input 5 V detect pin for port C in the HDMI interface. 144 DDCC_SDA Digital I/O HDCP slave serial clock port C. DDCC_SDA is a 3.3 V input/output that is 5 V tolerant. PIN CONFIGURATIONS SYMBOL DESCRIPTION CS#Chip Select SI/SIO0 Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for Dual Output mode) SO/SIO1 Serial Data Output (for 1 x I/O)/ Serial Data Output (for Dual Output mode) Clock Input WP#Write protection HOLD# Hold, to pause the device without deselecting the device VCC GNDGround PIN DESCRIPTION 8-PIN SOP (200mil) 93 CS497024CVZ (DIGITAL : IC741) 94 CS497024CVZ Block diagram MX25L8006EM2I-12G (DIGITAL : IC742) CS#1 2 3 4 8 7 6 5 SO/SIO1 WP# GND VCC HOLD# SCLK SI/SIO0 SYMBOL CS# SI/SIO0 SO/SIO1 SCLK WP# HOLD# VCC GND Chip Select Serial Data Input (for 1 x I/O)/ Serial Data Input & Output (for Dual Output mode) Serial Data Output (for 1 x I/O)/ Serial Data Output (for Dual Output mode) Clock Input Write protection + 3.3V Power Supply Ground Hold, to pause the device without deselecting the device DESCRIPTION PIN DESCRIPTION 95 M12L16161A5TG (DIGITAL : IC743) M12L16161A5TG Terminal Functions Pin Name Input Function CLKSystem ClockActive on the positive going edge to sample all inputs. CSChip Select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM. CKEClock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 A10/AP Address Row / column addresses are multiplexed on the same pins. Row address : RA0 RA10, column address : CA0 CA7 BABank Select Address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RASRow Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CASColumn Address Strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WEWrite EnableEnables write operation and row precharge. Latches data in starting from CAS , WE active. L(U)DQMData Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. DQ015Data Input / OutputData inputs/outputs are multiplexed on the same pins. VDD/VSSPower Supply/GroundPower and ground for the input buffers and the core logic. VDDQ/VSSQData Output Power/GroundIsolated power supply and ground for the output buffers to provide improved noise immunity. N.C/RFUNo Connection/ Reserved for Future Use This pin is recommended to be left No Connection on the device. 96 CS42528-CQ (DIGITAL : IC744) CS42528 Block diagram 97 CS42528 Terminal Functions 98 TC74VHC157FT (DIGITAL : IC745-747) EN5339QI (DIGITAL : IC751-753) TC74VHC157F/FN/FT/FK 2007-10-01 2 Pin Assignment IEC Logic Symbol Truth Table Inputs ST SELECT A B Output H X X X L L L L X L L L H X H L H X L L L H X H H X: Dont care (1) (15) (2) (5) (3) 1A 2A 1B (6) (10) 3A 2B (4) (9) 1Y 3Y (7) (12) 2Y 4Y EN SELECT ST 3B (14) (13) 4A 4B G1 (11) 1MUX 1 4A VCC 16 4B 15 14 13 12 11 10 1 2 3 4 5 6 7 1Y 2A 2B 2Y GND 4Y 8 3Y 9 3A 3B (top view) 1A 1B SELECT ST A S G B A Y B A Y B A Y BY 06903March 30, 2012Rev: A EN5339QI Enpirion 2012 all rights reserved, E&OE , Page 2 Part Number Package Markings Temp Rating ( C) Package Description EN5339QI EN5339 -40 to +85 24-pin (4mm x 6mm x 1.1mm) QFN T&R EN5339QI-E EN5339 QFN Evaluation Board Packing and Marking Information: Figure 3: Pin Out Diagram (Top View) NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. NOTE B: Grey area highlights exposed metal on the bottom of the package that is not to be mechanically or electrically connected to the PCB. There should be no traces on PCB top layer under these keep out areas. NOTE C: White dot on top left is pin 1 indicator on top of the device package. PIN NAME FUNCTION 1, 21-24 NC(SW) NO CONNECT: These pins are internally connected to the common switching node of the internal MOSFETs. They must be soldered to PCB but not be electrically connected to any external signal, ground, or voltage. Failure to follow this guideline may result in device damage. 2-3, 8-9 PGND Input and output power ground. Connect these pins to the ground electrode of the input and output filter capacitors. See VOUT, PVIN descriptions and Layout Recommendation for more details. 4-7 VOUT Regulated converter output. Connect to the load and place output filter capacitor(s) between these pins and PGND pins 7 and 8. See layout recommendation for details 10 TST2 Test Pin. For Enpirion internal use only. Connect to AVIN at all times. 11 TST1 Test Pin. For Enpirion internal use only. Connect to AVIN at all times. 99 NJU72340A (DIGITAL :IC761) NJU72340A Terminal Functions 100 BX8804(USB : IC901) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AD04 AD03 VSS33 VDD33 AD02 AD01 AD00 D15 D7 D14 D6 D13 D5 D12 D4 D11 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 BA0 BA1 LDQM UDQM SDCSN VDD12 VSS12 CKE RASN VDD33 VSS33 SDCLK CASN WEN 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 ADIN3 ADIN4 PLL1VDD12 PLL1VSS12 PLL2VDD12 PLL2VSS12 PLL3VDD12 PLL3VSS12 USBVSS33 USBDM USBDP USBVDD33 VSS33 VDD33 XO XI TEST VSS33 BX8804 ADIN2 NC VSS12 VDD12 D3 D10 D2 D9 D1 D8 D0 GP01 / EXT INT 1 GP00 / EXT INT 0 AVSS33 AVDD33 ADIN0 ADIN1 EAD17 / GP37 EAD18 / GP38 EAD19 / GP39 EAD20 / GP40 / Boot Mode EWEN / GP41 EOEN / G