HarmanKardon-AVR3550HD-avr-sm2维修电路原理图.pdf

1.1 Features TMP86F409NG9. 8bit Serial Expansion Interface (SEI): 1 channel(MSB/LSB selectable and max. 4Mbps at 16MHz)10.10-bit successive approximation type AD converter- Analog input: 6 ch11. Key-on wakeup : 4 channels12. Clock operationSingle clock modeDual clock mode13. Low power consumption operationSTOP mode: Oscillation stops. (Battery/Capacitor back-up.)SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clockstop.)SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clockoscillate.)IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high fre-quency clock. Release by falling edge of the source clock which is set by TBTCR.IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interru-puts(CPU restarts).IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by inter-ruputs. (CPU restarts).SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low fre-quency clock.Release by falling edge of the source clock which is set by TBTCR.SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interru-put.(CPU restarts).SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock. Release byinterruput.14.Wide operation voltage: 4.5 V to 5.5 V at 16MHz /32.768 kHz 2.7 V to 5.5 V at 8 MHz /32.768 kHz 81AVR3550HD harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 TMP86F409NG 1.2Pin AssignmentFigure 1-1 Pin Assignment3231302928272625242322212019181712345678910111213141516 VSS XOUT TEST VDD(XTIN) P21(XTOUT) P22 RESET(STOP/INT5) P20(TXD) P00(SCLK) P02(MISO) P04(MOSI) P03 P14 P16P30 (TC3/PDO3/PWM3) P32 (AIN0) P33 (AIN1) P35 (AIN3/STOP3) P34 (AIN2/STOP2) P37 (AIN5/STOP5) P36 (AIN4/STOP4) P31 (TC4/PDO4/PWM4/PPG4) (RXD) P01 XINP15 P05 (SS) P06 (INT3/PPG) P07 (TC1/INT4) P12 (DVO) P10 (INT0) P13 P11 (INT1) 82AVR3550HD harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 1.3 Block Diagram TMP86F409NG 1.3Block DiagramFigure 1-2 Block Diagram83AVR3550HD harmanharman/kardon/kardon TMP86F409NG 1.4Pin Names and FunctionsThe TMP86F409NG has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pinfunctions in MCU mode. The serial PROM mode is explained later in a separate chapter.Table 1-1 Pin Names and Functions(1/2)Pin NamePin NumberInput/OutputFunctionsP07TC1INT421IOIIPORT07TC1 inputExternal interrupt 4 inputP06INT3PPG20IOIOPORT06External interrupt 3 inputPPG outputP05SS19IOIPORT05SEI master/slave select inputP04MISO14IOIOPORT04SEI master input, slave outputP03MOSI13IOIOPORT03SEI master input, slave outputP02SCLK12IOIOPORT02SEI serial clock input/output pinP01RXD11IOIPORT01UART data inputP00TXD10IOOPORT00UART data outputP1616IOPORT16P1517IOPORT15P1415IOPORT14P1318IOPORT13P12DVO24IOOPORT12Divider OutputP11INT123IOIPORT11External interrupt 1 inputP10INT022IOIPORT10External interrupt 0 inputP22XTOUT7IOOPORT22Resonator connecting pins(32.768kHz) for inputting external clockP21XTIN6IOIPORT21Resonator connecting pins(32.768kHz) for inputting external clockP20INT5STOP9IOIIPORT20External interrupt 5 inputSTOP mode release signal inputP37AIN5STOP532IOIIPORT37Analog Input5STOP5P36AIN4STOP431IOIIPORT36Analog Input4STOP484AVR3550HD harmanharman/kardon/kardon TMP86F409NGP35AIN3STOP330IOIIPORT35Analog Input3STOP3P34AIN2STOP229IOIIPORT34Analog Input2STOP2P33AIN128IOIPORT33Analog Input1P32AIN027IOIPORT32Analog Input0P31TC4PDO4/PWM4/PPG426IOIOPORT31TC4 inputPDO4/PWM4/PPG4 outputP30TC3PDO3/PWM325IOIOPORT30TC3 inputPDO3/PWM3 outputXIN2IResonator connecting pins for high-frequency clockXOUT3OResonator connecting pins for high-frequency clockRESET8IReset signalTEST4ITest pin for out-going test. Normally, be fixed to low.VDD5I+5VVSS1I0(GND)Table 1-1 Pin Names and Functions(2/2)Pin NamePin NumberInput/OutputFunctions85AVR3550HD harmanharman/kardon/kardon 3Revision 1.9256M Double Data Rate Synchronous DRAMA3S56D30ETPA3S56D40ETPPin Assignment (Top View) 66-pin TSOP123456789101112131415161718192021222324252627282930313233666564636261605958575655545352515049484746454443424140393837363534VDDDQ0VDDQDQ1DQ2VSSQDQ3DQ4VDDQDQ5DQ6VSSQDQ7NCVDDQLDQSNCVDDNCLDM/WE/CAS/RAS/CSNCBA0BA1A10/APA0A1A2A3VDDVSSDQ15VSSQDQ14DQ13VDDQDQ12DQ11VSSQDQ10DQ9VDDQDQ8NCVSSQUDQSNCVREFVSSUDM/CLKCLKCKENCA12A11A9A8A7A6A5A4VSS66pin TSOP(II)400mil widthx875mil length0.65mmLead PitchRowA0-12ColumnA0-9 (x8)A0-8 (x16)VDDDQ0VDDQNCDQ1VSSQNCDQ2VDDQNCDQ3VSSQNCNCVDDQNCNCVDDNCNC/WE/CAS/RAS/CSNCBA0BA1A10/APA0A1A2A3VDDVSSDQ7VSSQNCDQ6VDDQNCDQ5VSSQNCDQ4VDDQNCNCVSSQDQSNCVREFVSSDM/CLKCLKCKENCA12A11A9A8A7A6A5A4VSSx8x16CLK, /CLKCKE/CS/RAS/CAS/WEDQ0-15UDM, LDM DM DQ0-7UDQS, LDQS DQS : Master Clock: Clock Enable: Chip Select: Row Address Strobe: Column Address Strobe: Write Enable: Data I/O (x16) : Write Mask (x16): Write Mask (x8): Data I/O (x8) : Data Strobe (x16): Data Strobe (x8)A0-12BA0,1VddVddQVssVssQ: Address Input: Bank Address Input: Power Supply: Power Supply for Output: Ground: Ground for Output86AVR3550HD harman/kardonharman/kardon 4Revision 1.9256M Double Data Rate Synchronous DRAMA3S56D30ETPA3S56D40ETPPIN FUNCTIONCLK, /CLKInputClock: CLK and /CLK are differential clock inputs. All address and controlinput signals are sampled on the crossing of the positive edge of CLK andnegative edge of /CLK. Output (read) data is referenced to the crossings ofCLK and /CLK (both directions of crossing).CKEInputClock Enable: CKE controls internal clock. When CKE is low, internal clockfor the following cycle is ceased. CKE is also used to select auto / self refresh.After self refresh mode is started, CKE becomes asynchronous input. Self refreshis maintained as long as CKE is low./CSInputChip Select: When /CS is high, any command means No Operation./RAS, /CAS, /WEInputCombination of /RAS, /CAS, /WE defines basic commands.A0-12InputA0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. BA0,1InputDQ0-7 (x8),DQ0-15 (x16),Input / OutputDQS (x8)Vdd, VssPower SupplyPower Supply for the memory array and peripheral circuitry.VddQ, VssQPower SupplyVddQ and VssQ are supplied to the Output Buffers only.Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data Input/Output: Data busData Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15SYMBOLTYPEDESCRIPTIONDM (x8)InputInput Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQand DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7; UDM corresponds to the data on DQ8-DQ15.Input / OutputVrefInputSSTL_2 reference voltage.UDQS, LDQS (x16)UDM, LDM (x16)87AVR3550HD harman/kardonharman/kardon 5Revision 1.9256M Double Data Rate Synchronous DRAMA3S56D30ETPA3S56D40ETPBLOCK DIAGRAM/CS/RAS /CAS/WEDMMemoryArrayBank #0DQ0 - 7I/O BufferMemoryArrayBank #1MemoryArrayBank #2MemoryArrayBank #3Mode RegisterControl CircuitryAddress BufferA0-12BA0,1Clock BufferCLKCKEControl Signal BufferDQS BufferDQSDLL/CLKA3S56D30ETPType Designation CodeThis rule is applied to only Synchronous DRAM family.Zentel DRAMSpeed GradePackage Type TP: TSOP(II)Process GenerationFunction Reserved for Future UseOrganization 2n3: x8DDR Synchronous DRAMDensity 56: 256M bitsInterface S:SSTL_3, _2Memory Style (DRAM)A 3 S 56 D 3 0 E TP G5 6: 166MHz CL=3.0/2.5, and 133MHz CL=2.05: 200MHz CL=3.0, 166MHz CL=2.5, and 133MHz CL=2.05E: 200MHz CL=3.0/2.5, and 133MHz CL=2.088AVR3550HD harman/kardonharman/kardon 6Revision 1.9256M Double Data Rate Synchronous DRAMA3S56D30ETPA3S56D40ETPBLOCK DIAGRAM/CS/RAS /CAS/WEUDM,LDMMemoryArrayBank #0DQ0 - 15I/O BufferMemoryArrayBank #1MemoryArrayBank #2MemoryArrayBank #3Mode RegisterControl CircuitryAddress BufferA0-12BA0,1Clock BufferCLKCKEControl Signal BufferDQS BufferUDQS, LDQSDLL/CLKA3S56D40ETPType Designation CodeThis rule is applied to only Synchronous DRAM family.Zentel DRAMSpeed GradePackage Type TP: TSOP(II)Process GenerationFunction Reserved for Future UseOrganization 2n4: x16DDR Synchronous DRAMDensity 56: 256M bitsInterface S:SSTL_3, _2Memory Style (DRAM)A 3 S 56 D 4 0 E TP G56: 166MHz CL=3.0/2.5, and 133MHz CL=2.05: 200MHz CL=3.0, 166MHz CL=2.5, and 133MHz CL=2.05E: 200MHz CL=3.0/2.5, and 133MHz CL=2.089AVR3550HD harman/kardonharman/kardon Excel Semiconductor inc.ES29LV320E32Mbit(4M x 8/2M x 16)CMOS 3.0 Volt-only, Boot Sector Flash MemoryGENERAL FEATURESSingle power supply operation - 2.7V 3.6V for read, program and erase operationsSector Structure - 8Kbyte x 8 boot sectors - 64Kbyte x 63 sectors - 256byte security sectorTop or Bottom boot block - ES29LV320ET for Top boot block device - ES29LV320EB for Bottom boot block deviceA 256 bytes of extra sector for security code - Factory locked - Customer lockable Package Options - 48-pin TSOP - 48-ball FBGA - Pb-free packages - All Pb-free products are RoHS-Compliant Low Vcc write inhibit Manufactured on 0.18um process technologyCompatible with JEDEC standards - Pinout and software compatible with single-power supply flash standardDEVICE PERFORMANCE Read access time - 70ns/90ns for normal Vcc range ( 2.7V 3.6V ) Program and erase time - Program time : 6us/byte, 8us/word ( typical ) - Accelerated program time : 4us/word ( typical ) - Sector erase time : 0.7sec/sector ( typical )Power consumption (typical values) - 15uA in standby or automatic sleep mode - 10mA active read current at 5MHz - 15mA active write current during program or eraseMinimum 100,000 program/erase cycles per sector20 Year data retention at 125oC SOFTWARE FEATURESErase Suspend / Erase ResumeData# poll and toggle for Program/erase statusCFI ( Common Flash Interface) supportedUnlock Bypass ProgramAutoselect modeAuto-sleep mode after tACC + 30nsHARDWARE FEATURESHardware reset input pin (RESET#) - Provides a hardware reset to device - Any internal device operation is terminated and the device returns to read mode by the resetReady/Busy# output pin (RY/BY#) - Provides a program or erase operational status about whether it is finished for read or still being progressedWP#/ACC input pin - Two outermost boot sectors are protected when WP# is set to low, regardless of sector protection - Program speed is accelerated by raising WP#/ACC to a high voltage (11.5V12.5V) Sector protection / unprotection (RESET# , A9 ) - Hardware method of locking a sector to prevent any program or erase operation within that sector - Two methods are provided : - In-system method by RESET# pin - A9 high-voltage method for PROM programmersTemporary Sector Unprotection (RESET# ) - Allows temporary unprotection of previously protected sectors to change data in-system 90AVR3550HD harman/kardonharman/kardon Excel Semiconductor inc.The ES29LV320 is a 32 megabit, 3.0 volt-only flashmemory device, organized as 4M x 8 bits (Bytemode) or 2M x 16 bits (Word mode) which is config-urable by BYTE#. Eight boot sectors and sixty threemain sectors with uniform size are provided :8Kbytes x 8 and 64Kbytes x 63. The device is man-ufactured with ESIs proprietary, high performanceand highly reliable 0.18um CMOS flash technology.The device can be programmed or erased in-sys-tem with standard 3.0 Volt Vcc supply ( 2.7V3.6V)and can also be programmed in standard EPROMprogrammers. The device offers minimum endur-ance of 100,000 program/erase cycles and morethan 10 years of data retention.The ES29LV320 offers access time as fast as 70nsor 90ns, allowing operation of high-speed micropro-cessors without wait states. Three separate controlpins are provided to eliminate bus contention : chipenable (CE#), write enable (WE#) and outputenable (OE#). All program and erase operation are automaticallyand internally performed and controlled by embed-ded program/erase algorithms built in the device.The device automatically generates and times thenecessary high-voltage pulses to be applied to thecells, performs the verification, and counts the num-ber of sequences. Some status bits (DQ7, DQ6 andDQ5) read by data# polling or toggling betweenconsecutive read cycles provide to the users theinternal status of program/erase operation: whetherit is successfully done or still being progressed.Extra Security Sector of 256 bytesIn the device, an extra security sector of 256 bytes isprovided to customers. This extra sector can beused for various purposes such as storing ESN(Electronic Serial Number) or customers securitycodes. Once after the extra sector is written, it canbe permanently locked by the device manufacturer(factory-locked) or a customer(customer-lockble).At the same time, a lock indicator bit (DQ7) is per-manently set to a 1 if the part is factory- locked, orset to 0 if it is customer-lockable. Therefore, this lockindicator bit (DQ7) can be properly used to avoidthat any customer-lockable part is used to replace afactory-locked part. The extra security sector is anextra memory space for customers when it is usedas a customer-lockable version. So, it can be readand written like any other sectors. But it should benoted that the number of E/W(Erase and Write)cycles is limited to 300 times (maximum) only in theSecurity Sector. Special services such as ESN and factory-lock areavailable to customers (ESIs Special-Code service) The ES29LV320 is completely compatible with theJEDEC standard command set of single power sup-ply Flash. Commands are written to the internalcommand register using standard write timings ofmicroprocessor and data can be read out from thecell array in the device with the same way as used inother EPROM or flash devices.GENERAL PRODUCT DESCRIPTIONES29LV320E91AVR3550HD harman/kardonharman/kardon PRODUCT SELECTOR GUIDEFamily Part NumberES29LV320EVoltage Range2.7V 3.6 VSpeed Option7090Max Access Time (ns)7090CE# Access (ns)7090OE# Access (ns)3040CommandRegisterAnalog BiasGeneratorAddress LatchBYTE#CE#OE#ARESET#VccVssChip EnableOutput EnableLogicVcc DetectorTimer/CounterY-DecoderX-DecoderY-DecoderCell ArrayData Latch/Sense AmpsInput/OutputBuffersSector SwitchesDQ0-DQ15(A-1)RY/BY#WriteStateMachineWE#FUNCTION BLOCK DIAGRAMES29LV320E92AVR3550HD harman/kardonharman/kardon Excel Semiconductor inc.PIN DESCRIPTIONPinDescriptionA0-A2021 AddressesDQ0-DQ1415 Data Inputs/OutputsDQ15/A-1DQ15 (Data Input/Output, Word Mode)A-1 (LSB Address Input, Byte Mode)CE#Chip EnableOE#Output EnableWE#Write EnableWP#/ACCHardware Write Protect/Accelerati