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Philips Semiconductors RF Communications ProductsProduct specification NE/SA572Programmable analog compandor 2October 7, 1987853-0813 90829 DESCRIPTION The NE572 is a dual-channel, high-performance gain control circuit in which either channel may be used for dynamic range compression or expansion. Each channel has a full-wave rectifier to detect the average value of input signal, a linearized, temperature-compensated variable gain cell (G) and a dynamic time constant buffer. The buffer permits independent control of dynamic attack and recovery time with minimum external components and improved low frequency gain control ripple distortion over previous compandors. The NE572 is intended for noise reduction in high-performance audio systems. It can also be used in a wide range of communication systems and video recording applications. FEATURES Independent control of attack and recovery time Improved low frequency gain control ripple Complementary gain compression and expansion with external op amp Wide dynamic rangegreater than 110dB Temperature-compensated gain control Low distortion gain cell Low noise6V typical Wide supply voltage range6V-22V System level adjustable with external components APPLICATIONS Dynamic noise reduction system Voltage control amplifier Stereo expandor Automatic level control High-level limiter Low-level noise gate State variable filter PIN CONFIGURATION 1 2 3 4 5 6 7 89 10 11 12 13 14 16 15 D1, N, F Packages TRACK TRIM A RECOV. CAP A RECT. IN A ATTACK CAP A THD TRIM A GND G OUT A G IN A TRACK TRIM B RECOV. CAP B RECT. IN B ATTACK CAP B THD TRIM B G OUT B G IN B VCC NOTE: 1. D package released in large SO (SOL) package only. ORDERING INFORMATION DESCRIPTIONTEMPERATURE RANGEORDER CODEDWG # 16-Pin Plastic Small Outline (SO)0 to +70CNE572D0005 16-Pin Plastic Dual In-Line Package (DIP)0 to +70CNE572N0406 16-Pin Plastic Small Outline (SO)40 to +85CSA572D0005 16-Pin Ceramic Dual In-Line Package (Cerdip)40 to +85CSA572F0582 16-Pin Plastic Dual In-Line Package (DIP)40 to +85CSA572N0406 ABSOLUTE MAXIMUM RATINGS SYMBOLPARAMETERRATINGUNIT VCCSupply voltage22VDC TAOperating temperature range NE5720 to +70C SA57240 to +85 PDPower dissipation500mW RadioFans.CN 收音机爱 好者资料库 Philips Semiconductors RF Communications ProductsProduct specification NE/SA572Programmable analog compandor October 7, 19873 BLOCK DIAGRAM (7,9) (6,10) (3,13) (16) (8)(4,12)(2,14) (1,15) (5,11) GAIN CELL RECTIFIER P.S. 6.8k 10k BUFFER10k 270 500 R1 G + + DC ELECTRICAL CHARACTERISTICS Standard test conditions (unless otherwise noted) VCC=15V, TA=25C; Expandor mode (see Test Circuit). Input signals at unity gain level (0dB) = 100mVRMS at 1kHz; V1 = V2; R2 = 3.3k; R3 = 17.3k. SYMBOLPARAMETERTEST CONDITIONSNE572SA572UNIT MinTypMaxMinTypMax VCCSupply voltage622622VDC ICCSupply currentNo signal66.3mA VRInternal voltage reference2.32.52.72.32.52.7VDC THD Total harmonic distortion (untrimmed) 1kHz CA=1.0F0.21.00.21.0% THD Total harmonic distortion (trimmed) 1kHz CR=10F0.050.05% THD Total harmonic distortion (trimmed) 100Hz0.250.25% No signal output noise Input to V1 and V2 grounded (2020kHz) 625625V DC level shift (untrimmed) Input change from no signal to 100mVRMS 20502050mV Unity gain level10+11.50+1.5dB Largesignal distortionV1=V2=400mV0.73.00.73% Tracking error (measured relative to value at unityRectifier input gain)=V2=+6dB V1=0dB0.20.2 VOVO (unity gain)dBV2=30dB V1=0dB0.51.50.52.5dB V2dB+0.8+1.6 Channel crosstalk 200mVRMS into channel A, measured output on channel B 6060dB PSRR Power supply rejection ra- tio 120Hz7070dB RadioFans.CN 收音机爱 好者资料库 Philips Semiconductors RF Communications ProductsProduct specification NE/SA572Programmable analog compandor October 7, 19874 TEST CIRCUIT BUFFER RECTIFIER NE5234 +15V 15V (7,9) (2,14) (4,12) 6.8k (5,11) (6,10) (8) (1,15) (16) 3.3k(3,13) G V1 V2 V0 270pF 82k 2.2k 17.3k 1% 2.2F 22F 2.2F 22F .1F 1F 2.2F 5 = 10F R3 1% R2 100 1k+ + + + AUDIO SIGNAL PROCESSING IC COMBINES VCA AND FAST AT- TACK/SLOW RECOVERY LEVEL SENSOR In high-performance audio gain control applications, it is desirable to independently control the attack and recovery time of the gain control signal. This is true, for example, in compandor applications for noise reduction. In high end systems the input signal is usually split into two or more frequency bands to optimize the dynamic behavior for each band. This reduces low frequency distortion due to control signal ripple, phase distortion, high frequency channel overload and noise modulation. Because of the expense in hardware, multiple band signal processing up to now was limited to professional audio applications. With the introduction of the Signetics NE572 this high-performance noise reduction concept becomes feasible for consumer hi fi applications. The NE572 is a dual channel gain control IC. Each channel has a linearized, temperature-compensated gain cell and an improved level sensor. In conjunction with an external low noise op amp for current-to-voltage conversion, the VCA features low distortion, low noise and wide dynamic range. The novel level sensor which provides gain control current for the VCA gives lower gain control ripple and independent control of fast attack, slow recovery dynamic response. An attack capacitor CA with an internal 10k resistor RA defines the attack time tA. The recovery time tR of a tone burst is defined by a recovery capacitor CR and an internal 10k resistor RR. Typical attack time of 4ms for the high-frequency spectrum and 40ms for the low frequency band can be obtained with 0.1F and 1.0F attack capacitors, respectively. Recovery time of 200ms can be obtained with a 4.7F recovery capacitor for a 100Hz signal, the third harmonic distortion is improved by more than 10dB over the simple RC ripple filter with a single 1.0F attack and recovery capacitor, while the attack time remains the same. The NE572 is assembled in a standard 16-pin dual in-line plastic package and in oversized SOL package. It operates over a wide supply range from 6V to 22V. Supply current is less than 6mA. The NE572 is designed for consumer application over a temperature range 0-70 The SA572 is intended for applications from 40C to +85C. NE572 BASIC APPLICATIONS Description The NE572 consists of two linearized, temperature-compensated gain cells (G), each with a full-wave rectifier and a buffer amplifier as shown in the block diagram. The two channels share a 2.5V common bias reference derived from the power supply but otherwise operate independently. Because of inherent low distortion, low noise and the capability to linearize large signals, a wide dynamic range can be obtained. The buffer amplifiers are provided to permit control of attack time and recovery time independent of each other. Partitioned as shown in the block diagram, the IC allows flexibility in the design of system levels that optimize DC shift, ripple distortion, tracking accuracy and noise floor for a wide range of application requirements. Gain Cell Figure 1 shows the circuit configuration of the gain cell. Bases of the differential pairs Q1-Q2 and Q3-Q4 are both tied to the output and inputs of OPA A1. The negative feedback through Q1 holds the VBE of Q1-Q2 and the VBE of Q3-Q4 equal. The following relationship can be derived from the transistor model equation in the forward active region. ?VBE Q3Q4 ? ?BE Q1Q2 (VBE = VT IIN IC/IS) RadioFans.CN 收音机爱 好者资料库 VREF THD TRIM V+ R1 6.8k 1 2IG ? 1 2IO I1 140A 280A I2 IG IO Q4 Q3Q1 Q2 VIN + A1 Figure 1. Basic Gain Cell Schematic Philips Semiconductors RF Communications ProductsProduct specification NE/SA572Programmable analog compandor October 7, 19875 VTIn ? 1 2IG ? 1 2 IO IS ? ? VTIn ? 1 2 IG ? 1 2IO IS ? where IIN? VIN R1 R1 = 6.8k I1 = 140A I2 = 280A VTIn ? I1 ? IIN IS ? ? VTIn ? I2 ? I1 ? IIN IS ? (2) where IIN? VIN R1 R1 = 6.8k I1 = 140A I2 = 280A IO is the differential output current of the gain cell and IG is the gain control current of the gain cell. If all transistors Q1 through Q4 are of the same size, equation (2) can be simplified to: IO? 2 I2 ? IIN ? IG ? 1 I2 ? I2 ? 2I1 ? ? IG(3) The first term of Equation 3 shows the multiplier relationship of a linearized two quadrant transconductance amplifier. The second term is the gain control feedthrough due to the mismatch of devices. In the design, this has been minimized by large matched devices and careful layout. Offset voltage is caused by the device mismatch and it leads to even harmonic distortion. The offset voltage can be trimmed out by feeding a current source within 25A into the THD trim pin. The residual distortion is third harmonic distortion and is caused by gain control ripple. In a compandor system, available control of fast attack and slow recovery improve ripple distortion significantly. At the unity gain level of 100mV, the gain cell gives THD (total harmonic distortion) of 0.17% typ. Output noise with no input signals is only 6V in the audio spectrum (10Hz-20kHz). The output current IO must feed the virtual ground input of an operational amplifier with a resistor from output to inverting input. The non-inverting input of the operational amplifier has to be biased at VREF if the output current IO is DC coupled. Rectifier The rectifier is a full-wave design as shown in Figure 2. The input voltage is converted to current through the input resistor R2 and turns on either Q5 or Q6 depending on the signal polarity. Deadband of the voltage to current converter is reduced by the loop gain of the gain block A2. If AC coupling is used, the rectifier error comes only from input bias current of gain block A2. The input bias current is typically about 70nA. Frequency response of the gain block A2 also causes second-order error at high frequency. The collector current of Q6 is mirrored and summed at the collector of Q5 to form the full wave rectified output current IR. The rectifier transfer function is IR? VIN ? VREF R2 (4) If VIN is AC-coupled, then the equation will be reduced to: IRAC? VIN(AVG) R2 The internal bias scheme limits the maximum output current IR to be around 300A. Within a 1dB error band the input range of the rectifier is about 52dB. VIN VREF V+ A2 + R2 Q6 Q5 D7 IR? VIN ? VREF R2 Figure 2. Simplified Rectifier Schematic Q8Q9 Q10 Q17 X2 Q16 X2 Q18 10k D13 Q14 CR D15 A3 10k D11 D12 CA TRACKING TRIM IR1 IR2 IQ = 2IR2 V+ IR? VIN R + Figure 3. Buffer Amplifier Schematic Philips Semiconductors RF Communications ProductsProduct specification NE/SA572Programmable analog compandor October 7, 19876 Buffer Amplifier In audio systems, it is desirable to have fast attack time and slow recovery time for a tone burst input. The fast attack time reduces transient channel overload but also causes low-frequency ripple distortion. The low-frequency ripple distortion can be improved with the slow recovery time. If different attack times are implemented in corresponding frequency spectrums in a split band audio system, high quality performance can be achieved. The buffer amplifier is designed to make this feature available with minimum external components. Referring to Figure 3, the rectifier output current is mirrored into the input and output of the unipolar buffer amplifier A3 through Q8, Q9 and Q10. Diodes D11 and D12 improve tracking accuracy and provide common-mode bias for A3. For a positive-going input signal, the buffer amplifier acts like a voltage-follower. Therefore, the output impedance of A3 makes the contribution of capacitor CR to attack time insignificant. Neglecting diode impedance, the gain Ga(t) for G can be expressed as follows: Ga(t) ? (GaINT ? GaFNLe ? t ? A ? GaFNL GaINT=Initial Gain GaFNL=Final Gain A=RA CA=10k CA where A is the attack time constant and RA is a 10k internal resistor. Diode D15 opens the feedback loop of A3 for a negative-going signal if the value of capacitor CR is larger than capacitor CA. The recovery time depends only on CR RR. If the diode impedance is assumed negligible, the dynamic gain GR (t) for G is expressed as follows. GR(t) ? (GRINT ? GRFNLe ? t ? R ? GRFNL GR(t)=(GR INTGR FNL) e +GR FNL R=RR CR=10k CR where R is the recovery time constant and RR is a 10k internal resistor. The gain control current is mirrored to the gain cell through Q14. The low level gain errors due to input bias current of A2 and A3 can be trimmed through the tracking trim pin into A3 with a current source of 3A. Basic Expandor Figure 4 shows an application of the circuit as a simple expandor. The gain expression of the system is given by Philips Semiconductors RF Communications ProductsProduct specification NE/SA572Programmable analog compandor October 7, 19877 VOUT VIN ? 2 I1 ? R3 ? VIN(AVG) R2 ? R1 (5) (I1=140A) Both the resistors R1 and R2 are tied to internal summing nodes. R1 is a 6.8k internal resistor. The maximum input current into the gain cell can be as large as 140A. This corresponds to a voltage level of 140A 6.8k=952mV peak. The input peak current into the rectifier is limited to 300A by the internal bias system. Note that the value of R1 can be increased to accommodate higher input level. R2 and R3 are external resistors. It is easy to adjust the ratio of R3/R2 for desirable system voltage and current levels. A small R2 results in higher gain control current and smaller static and dynamic tracking error. However, an impedance buffer A1 may be necessary if the input is voltage drive with large source impedance. The gain cell output current feeds the summing node of the external OPA A2. R3 and A2 convert the gain cell output current to the output voltage. In high-performance applications, A2 has to be low-noise, high-speed and wide band so that the high-performance output of the gain cell will not be degraded. The non-inverting input of A2 can be biased at the low noise internal reference Pin 6 or 10. Resistor R4 is used to bias up the output DC level of A2 for maximum swing. The output DC level of A2 is given by VODC?VREF ? 1 ? R3 R4 ? ? VB R3 R4 (6) VB can be tied to a regulated power supply for a dual supply system and be grounded for a single supply system. CA sets the attack time constant and CR sets the recovery time constant. *5COL + A1 (7,9) R5 100k R2 3.3k (3,13) (8) (16) CACR (4,12) (2,14) 1k (6,10) R6 17.3k (5,11) BUFFER A2 R4R3 VOUTVIN CIN1 CIN2 CIN3 VREF R1 6.8k +VB +VCC G 10F1F 2.2F C1 2.2F 2.2F Figure 4. Basic Expandor Schematic (7,9) BUFFER VREF R1 6.8k G R4RDC1 RDC2 9.1k CDC 9.1k D1 D2 A1 R3 17.3k C1 1kR5 (6,10) (5,11) (2,14) (4,12) CRCA (8) (3,13) 3.3k R2 (16) CIN3 VCC 10F .1F C2 2.2F CIN1 VIN 10F 1F 2.2F CIN2 2.2F VOUT + Figure 5. Basic Compressor Schematic Philips Semiconductors RF Communications ProductsProduct specification NE/SA572Programmable analog compandor October 7, 19878 Basic Compressor Figure 5 shows the hook-up of the circuit as a compressor. The IC is put in the feedback loop of the OPA A1. The system gain expression is as follows: VOUT VIN ? ? I1 2 ? R2 ? R1 R3 ? VIN(AVG) ?