Akai-ADV-73-DR-Service-Manual(1) 电路图 维修手册.pdf

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LTPS LCD Specification Table of Contents NO.ItemPage Cover Sheet1 Table of Contents2 Record of Revision3 1Features4 2General Specifications4 3Input / Output Terminals5 4Absolute Maximum Ratings7 5Electrical Characteristics8 6Timing Chart9 7Optical Characteristics17 8Reliability19 9Handling Cautions20 10Mechanical Drawing21 11Packing Drawing22 Page: 3 Record of Revision RevIssued DateDescription 0.00Aug. 21, 2006 New create. Page: 4 1. FEATURES The 3.0” LCD module is the active matrix color TFT LCD module. LTPS (Low Temperature Poly Silicon) TFT technology is applied with vertical and horizontal drivers built on the panel. Both of horizontal and vertical scan are reversible and controlled by the serial interface commands. The product is designed for the requirement of the green product, and the specification complies with Toppolys “Green Product Chemical Substance Specification Standard Hand Book”. 2. GENERAL SPECIFICATIONS ItemDescriptionUnit Display Size (Diagonal)3.0Inch Aspect ratio16:9- Display TypeTransmissive- Active Area (HxV)65.31 x 36.84mm Number of Dots (HxV)960 x 240Dot Dot Pitch (HxV)0.068 x 0.1535mm Color ArrangementRGB Delta- Color Numbers16Million- NTSC40% Outline Dimension (HxVxT)75.31x43.44x2.58*(Approx.)mm WeightTBDG Panel surface treatmentHard Coating (3H)- *Exclude FPC and protrusions. Page: 5 Recommend connector: Compatible with JAE IL-FHJ-39S-HF-A1 PinSymbolI/ODescriptionRemark 1CP3CCapacitor for charge pump 2CP4CCapacitor for charge pump 3CP5CCapacitor for charge pump 4CP6CCapacitor for charge pump 5CP7CCapacitor for charge pump 6CP8CCapacitor for charge pump 7NC-No connection 8PCDLCCapacitor for pre-charge data signal low 9PCDHCCapacitor for pre-charge data signal high 10VCOMLCCapacitor for VCOM low 11VCOMHCCapacitor for VCOM high 12AGND-Analog ground 13PVDDCRegulation capacitor for charge pump 14AVDDCRegulation capacitor for analog voltage 15CP1CCapacitor for charge pump 16CP2CCapacitor for charge pump 17PWMOPower transistor gate signal for the boost converter 18FBIMain boost regulator feedback input 19LED-LED power: cathode 20LED+-LED power: anode Note 3-1 21NC-No connection 22GND-Ground 23VCC-Power supply 24VDIVertical sync input 25HDIHorizontal sync input 26DCLKIClock signal, latch data onto line latches at the rising edge 27DIN0IData input 28DIN1IData input 29DIN2IData input 30DIN3IData input 31DIN4IData input Page: 6 32DIN5IData input 33DIN6IData input 34DIN7IData input 35SDAI/O Serial interface data line 36SCLISerial interface clock line 37SCENISerial interface chip enable line 38SHDBISleep mode setting pin 39GRESTBIGlobal reset pin Note 3-1: The figure below shows the connection of backlight LED. Page: 7 Ta = 25 ItemSymbolMINMAXUnitRemark Logic Power Supply VoltageVCC-0.54.5V Input Signal VoltageVIN10VCCV VD, HD, DCLK, DIN0:7, SDA, SCL, SCEN, SHDB, GRESTB Back Light Forward CurrentIF-25mA Operating TemperatureTOPR-10+60 Storage TemperatureTSTG-30+80 Page: 8 GND=0V, Ta=25 ItemSymbolMINTYPMAXUnitRemark Power Supply VoltageVCC2.853.33.6VNote 5-1 Low LevelVILGND-0.2x Vcc*V Input Signal Voltage High LevelVIH0.8x Vcc*-Vcc*V VD, HD, DCLK, DIN0:7, SDA, SCL, SCEN, SHDB, GRESTB PWM Output VoltageVPWM0-Vcc*V Feedback VoltageVFB0.550.60.65VNote 5-2 Panel Power ConsumptionWP-70mW Vcc* =Vcc (TYP) Note 5-1: The Vcc power is provided for overall panel module supply voltage. Note 5-2: DC/DC feedback control voltage 5.2 Driving Backlight Ta=25 ItemSymbolMINTYPMAXUnitRemark Forward CurrentIF-2325mA Forward Current VoltageVF-9.610.8V Backlight Power ConsumptionWBL-221270mW Note 5-3 Note 5-3: Backlight driving circuit is recommended as the fix current circuit. Page: 9 6. TIMING CHART Serial RGBDummy or Serial-YUV 4:2:2 mode -Horizontal- (1) NTSC Mode: ParameterSymbolMINTYPMAXUnit DCLK FrequencyFDCLK-27-MHz Horizontal valid datathd-1440-DCLK 1 Horizontal Lineth-1716-DCLK HSYNC Pulse Widththpw11-DCLK Hsync blankingthp-240-DCLK Horizontal Front Porchthfp-36-DCLK Horizontal Dummy Timethdm-0-DCLK ParameterSymbolMINTYPMAXUnit DCLK FrequencyFDCLK-24.54-MHz Horizontal valid datathd-1280-DCLK 1 Horizontal Lineth-1560-DCLK HSYNC Pulse Widththpw11-DCLK Hsync blankingthp-240-DCLK Horizontal Front Porchthfp-40-DCLK Horizontal Dummy Timethdm-0-DCLK Page: 10 (2) PAL Mode: (3) QVGA Mode: ParameterSymbolMINTYPMAXUnit DCLK FrequencyFDCLK-27-MHz Horizontal valid datathd-1440-DCLK 1 Horizontal Lineth-1728-DCLK HSYNC Pulse Widththpw11-DCLK Hsync blankingthp-240-DCLK Horizontal Front Porchthfp-48-DCLK Horizontal Dummy Timethdm-0-DCLK ParameterSymbolMINTYPMAXUnit DCLK FrequencyFDCLK-24.38-MHz Horizontal valid datathd-1280-DC