Hitachi-HDR-081-Service-Manual(1) 电路图 维修手册.pdf

CAUTION: Before servicing this chassis, it is important that the service technician read the “Safety Precautions” and “Product Safety Notices” in this service manual. ATTENTION: Avant deffectuer lentretien du chssis, le technicien doit lire les Prcautions de scurit et les Notices de scurit du produit prsents dans le prsent manuel. VORSICHT: Vor ffnen des Gehuses hat der Service-Ingenieur die Sicherheitshinweise“ und Hinweise zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen. SERVICE MANUAL MANUEL DENTRETIEN WARTUNGSHANDBUCH Data contained within this Service manual is subject to alteration for improvement. Les donnes fournies dans le prsent manuel dentretien peuvent faire lobjet de modifications en vue de perfectionner le produit. Die in diesem Wartungshandbuch enthaltenen Spezifikationen knnen sich zwecks Verbesserungen ndern. SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT Digital Set Top Box October 2007 No. 0801 HDR081 HDR161 RadioFans.CN 收音机爱 好者资料库 SERVICE MANUAL TERRESTRIAL STB MODEL Page 2 RadioFans.CN 收音机爱 好者资料库 SERVICE MANUAL Page 3 TERRESTRIAL STB MODEL. 2 REVISION HISTORYREV 2.0 02/03/2007. 3 GENERAL DESCRIPTION. 4 T816 PROJECT HARDWARE BLOCK DIAGRAM . 4 16MB31-1 MAINBOARD. 5 STI5100 (IC101). 5 DDRAM HYNIX 512MBİTS . 11 HY29LV320 32 MBIT (2M X 16) LOW VOLTAGE FLASH MEMORY (IC1) . 12 16TUT36-2 TUNER BOARD . 13 STV0360/0361(COFDM DEMODULATORS IC FOR TERRESTRİAL TV SET-TOP BOX) . 13 TUNER (DTOS449IV241B-DTOS443PV241B). 15 16SC31-2 SCART BOARD . 17 STV6414AUDIO/VIDEO SWİTCH MATRİX(IC200). 17 16PW810-2 POWER BOARD . 18 16FP38-3 FRONT BOARD . 19 VFD DRİVER/CONTROLLER IC PT6311(IC2) . 19 USED IC LISTS. 22 MAINBOARD (16MB31-1) . 22 POWER BOARD (16PW810-2). 22 SCART BOARD (16SC31-2). 22 FRONT BOARD (16FP38-3). 22 CONNECTORS. 23 SCART CONNECTION . 24 TV SCART SOCKET . 24 VCR SCART SOCKET. 24 RS232 SERIAL PORT . 25 RCA (AUDIO AND COMPOSITE VIDEO) CONNECTOR . 25 TECHNICAL SPECIFICATIONS. 26 TROUBLE-SHOOTING . 28 PARTS LIST. 30 SCHEMATİCS. 32 16PW810-2 POWER BOARD SCHEMATIC. 32 16MB31-1 MAINBOARD SCHEMATIC . 33 16FP38-3 FRONT BOARD SCHEMATIC. 41 16SC31-2 AV SCHEMATIC . 42 EXPLODED VIEW. 31 16TUT36-2 TUNER SCHEMATIC . 44 RadioFans.CN 收音机爱 好者资料库 GENERAL DESCRIPTION Major functional blocks are discussed briefly in this section. A more detailed description is contained later in the document. BLOCK DIAGRAM Page 4 16mb31-1 Mainboard STI5100 (IC101) 1. Introduction The STi5100 is a low-cost Omega2 (The STBus multipath unified interconnect provides high on- chip bandwidth and low latency accesses between modules. The interconnect operates hierarchically, with latency-critical modules placed at the top level. The multipath router allows simultaneous access paths between modules, and simultaneous read and write phases from different transactions to and from the modules. Split transactions maximize the use of the available bandwidth.) MPEG device that delivers high performance and integrates features that provide an overall system cost reduction. The device implements a fully unified DDR SDRAM based memory architecture and integrates the Omega2 video decoder cell together with a blitter engine and a multichannel DMA controller to provide enhanced performance for graphics and real-time stream transfers. DVR applications are supported by a dual-stream deMUX and using an HDD connected either to the FMI or USB 2.0 port.The STi5100 includes transport stream routing and strobe decoding logic for DVB-CI and CableCard (formerly known as POD) modules to reduce implementation cost. 2. Technical Specification Features Enhanced ST20 32-bit VL-RISC CPU ? 243MHz, 8Kbyte ICache, 8Kbyte DCache, 4Kbyte SRAM Unified Memory Interface Dual Transport Stream Merger ? Supports DVB and DIRECTV . ? Integrated DES-ECB, DVB and ICAMdescramblers ? NDS RASP compliant ? Low cost DVB-CI and Cable Card support MPEG-2 MPML Video Decoder ? Trick modes including smooth fast forward andrewind Audio ? MPEG-1 layers I/II, MP3 ? Dolby . Digital decoding ? Dolby Pro Logic . compatible output ? PCM input, mixing and sample rate conversion ? SRS/TruSurrondXT . virtual surround sound ? Simultaneous MPEG audio decode and outputof Dolby streams Graphics/Display ? 4 display planes ? 2, 4 and 8 bpp CLUT graphics, 256 x 30 bits(AYCBCr) CLUT entries ? 16 bpp true color graphics ? Alpha blending, antialiasing, antiflutter,antiflicker filters PAL/NTSC/SECAM encoder ? RGB, CVBS, Y/C and YUV outputs with 10-bitDACs Page 5 SERVICE MANUAL ? CGMS, Teletext, WSS, VPS and close caption On-Chip Peripherals ? 4 ASCs (UARTS) ? 4 parallel 8-bit I/O banks ? 2 smartcard interfaces and clock generators ? 3 SSCs for IC/SPI master/slave interfaces ? Silicon Labs line side (DAA) interface ? High-speed USB OHCI/EHCI compliant host interface ? DiSEqC interface 3. Architecture overview The figure below shows the architecture of the Sti5100. This chapter gives a brief overview of each of the functional blocks of the STi5100. 4. STi5100 functional modules 4.1 Memory subsystem Page 6 SERVICE MANUAL The STi5100 has a local memory interface (LMI) and a flash and peripheral interface (FMI). The STi5100s local memory interface is used for all data requirements in unified memory applications, including graphics, video and audio buffers. It provides 16-bit wide DDR SDRAM support only at up to 166 MHz. The FMI provides support for 16-bit wide peripherals, flash and synchronous flash. Local memory interface (LMI) The LMI is a 16-bit wide DDR SDRAM interface with a peak bandwidth of 664 Mbyte/s (166 MHz). It supports one bank of 128-Mbit, 256-Mbit, or 512-Mbit DDR SDRAM. The LMI provides a fully cacheable address space for data and instructions, with data cacheability controlled in 512 Kbyte blocks for up to 8 Mbytes. Flash and peripheral memory interface (FMI) The FMI provides a glueless interface to SRAM, flash, SFlash and peripherals, in up to four configurable banks over a 16-bit wide interface. Bus cycle strobe timings can be programmed from 0 to 15 phases for slower peripherals. The FMI output drive of the STi5100/STi5101 is programmable on a bus- by-bus basis. Support is provided for connection to an ATAPI HDD. 4.2 Transport stream processing The STi5100 supports dual independent transport stream inputs using an SRAM-based packet merger and a single programmable transport interface (PTI). The merger buffers a packet pair per channel. The incoming transport packets are tagged with a source ID and a time stamp. Programmable transport interface (PTI) The PTI performs transport-stream descrambling, demultiplexing and data filtering. PESdata is transferred by DMA to audio and video decoders using circular buffers. Section data is transferred by DMA to separate buffers for further processing by the CPU. DIRECTV and DVB transport streams can be handled by the PTI with data rates up to 138 Mbit/s. The PTI performs PID filtering to select audio, video and data packets to be processed. 96 PID slots can be supported by the PTI. The PTI can descramble streams using the following ciphers: ? DES-ECB, ? DES-CBC including DVS-042 and cipher text stealing termination block handling, ? DVB-CSA, ? NDS specific streams can also be supported for integrated ICAM functionality. The PTI has a section filter core that filters DVB and DIRECTV standard sections. Four filtering modes are available: ? wide match mode: 48x 16-byte filters, ? long match mode: 96x 8-byte filters, ? positive/negative mode: 48x 8-byte filters with positive/negative filtering at the bit level. Matching sections are transferred to memory buffers for processing by software. When the PTI is required to output a transport stream, it can output the entire transport stream or selected packets filtered by PID. A latency counter is provided to ensure packet timing is preserved. Packet substitution can also be performed. 4.3 Audio subsystem The audio subsystem supports multichannel audio decoding and mixing with internal PCM files. Decoding of MPEG-1 layers I, II, MP3 and Dolby Digital stereo are supported.Decoded multichannel Page 7 SERVICE MANUAL audio is downmixed before emerging as stereo or Dolby Pro Logic compatible encoded audio. Simultaneous MPEG audio decoding and output of Dolby streams on the S/PDIF is also supported. SRS Labs TruSurroundXT is also provided for two speaker virtual surround sound. The integrated DACs provide analog stereo output directly from the device using a single-ended interface.Multichannel streams can be passed through to the IEC958 output for external decoding. Audio sample rates of 32 kHz, 44.1 kHz and 48 kHz are supported.The audio digital-to-analog converter is a high performance stereo audio converter operating at 256 Fs system clock using single-ended voltage. This DAC accepts a 24-bit input data in I 2 S format from the audio decoder macro block and converts them into up to 2 Vrms output voltage. Digitized analog audio can also be input to the STi5100 using the PCM input interface and buffered in memory via DMA. 26/830 STMicroelectronics Confidential 7603604B The audio subsystem consists of the following units. ? Audio datastream controller The audio datastream controller receives, buffers and reformats audio data. It handles up to three audio data flows concurrently. It receives a raw PCM stream from an external source via the PCM input interface or receives a compressed data stream from an internal source such as the PTI and stores this in a memory buffer via DMA. This is used to buffer and play the main audio for the digital or analog program. It receives a PCM file or stream from a memory buffer via DMA and delivers this to the audio decoders second input for sample rate conversion and mixing