Sony-CDPM305-cd-sm 电路图 维修手册.pdf

MICROFILM CDP-M205/M305 Model Name Using Similar MachanismCDP-M201/M301 CD Mechanism TypeCDM14-5BD29B Base Unit TypeBU-5BD29B Optical Pick-up TypeKSS-213B/K-N COMPACT DISC PLAYER Photo : CDP-M305 AEP Model UK Model CDP-M205/M305 E Model CDP-M305 SERVICE MANUAL SPECIFICATIONS RadioFans.CN 收音机爱 好者资料库 2 SAFETY-RELATED COMPONENT WARNING! COMPONENTS IDENTIFIED BY MARK ! OR DOTTED LINE WITH MARK ! ON THE SCHEMATIC DIAGRAMS AND IN THE PARTS LIST ARE CRITICAL TO SAFE OPERATION. REPLACE THESE COMPONENTS WITH SONY PARTS WHOSE PART NUMBERS APPEAR AS SHOWN IN THIS MANUAL OR IN SUPPLEMENTS PUBLISHED BY SONY. MODEL NO. CDP-M205 CDP-M305 COMPACT DISC PLAYER SERIAL NO. MADE IN JAPAN AEP, UK model : AC : 220230V50/60Hz 10W E model : AC : 110120V, 220240V Adjustable 50/60Hz 10W Specifications . 1 1.GENERAL Location and Function of Controls . 3 2.SERVICING NOTE. 4 3.DISASSEMBLY . 5 4.ELECTRICAL ADJUSTMENTS . 6 5.DIAGRAMS 5-1. IC Pin Function. 7 5-2. Printed Wiring Boards BD Section .11 5-3. Schematic Diagram BD Section . 13 5-4. Schematic Diagram Main Section . 17 5-5. Printed Wiring Boards Main Section . 21 6.EXPLODED VIEWS 6-1. Main Section. 26 6-2. CD Block Section . 27 6-3. Optical Pick-up Block Section (BU-5BD29B). 28 7.ELECTRICAL PARTS LIST . 29 TABLE OF CONTENTS WARNING To prevent fire or shock hazard, do not expose the unit to rain on moisture. To avoid electrical shock, do not open the cabinet. Refer servicing to qualified personnel only. The following caution label is located inside of the unit. This appliance is classified as a CLASS 1 LASER product. The CLASS 1 LASER PRODUCT MARKING is located on the rear exterior. Laser component in this product is capable of emitting radiation exceeding the limit for Class 1. MODEL IDENTIFICATION RadioFans.CN 收音机爱 好者资料库 3 SECTION 1 GENERAL LOCATION AND FUNCTION OF CONTROLS This section is extracted from instruction manual. 123456! 78 !09 9P(PAUSE) button 0(PLAY) button !DISPLAY window !REMOTE senser (CDP-M305 only) !PEAK SEARCH button !REPEAT button !TIME button !VOLTAGE selector (Singapore model) 1POWER switch 2CONTINUE button 3SHUFFLE button 4PROGRAM button 5DISK tray 6OPEN/CLOSE button 70/) (MANUAL SEARCH) buttons =/+(AMS : AUTOMATIC MUSIC SENSOR) buttons 8p(STOP) button 1 2 3 4 5 6 7 8 ! ! ! ! ! 0 9 9=/+(AMS : AUTOMATIC MUSIC SENSOR) buttons 0(PLAY) button !REPEAT button !TIME button !10 (OVER 10) button !NUMBER buttons !CONTINUE button 1SHUFFLE button 2PROGRAM button 3CLEAR button 4CHECK button 5FADER button 6p(STOP) button 7P(PAUSE) button 80/)(MANUAL SEARCH) buttons Front Panel Remote Commander (CDP-M305 only) RadioFans.CN 收音机爱 好者资料库 4 SECTION 2 SERVICING NOTE HOW TO OPEN THE DISC TRAY WHEN POWER SWITCH TURNS OFF Caution : When you work, keep the set horizontal. 1 Turn in the direction of the arrow 5 SECTION 3 DISASSEMBLY Note : Follow the disassembly procedure in the numerical order given. 3-1. PANEL, FRONT REMOVAL 2 5 5 6 Panel, Front 3 Wire (Flat type) (21core) Panel, Loading 3-2. CD MECHANISM SECTION REMOVAL 3 Wire (Flat type) (19 core) 2 4 CN151 (5P) CD mechanism section 1 Three screws (+BVTP 3x8 TYPE2 N-S) Chassis assy 4 Two screws (+BVTP 3x8TYPE2 N-S) 1 Turn in the direction of the arrow (Refer to page 4) 6 SECTION 4 ELECTRICAL ADJUSTMENTS oscilloscope BD board TP (RF) TP (VC) CD SECTION Note: 1. CD Block is basically constructed to operate without adjustment. Therefore, check each item in order given. 2. Use YEDS-18 disc (3-702-101-01) unless otherwise indicated. 3. Use an oscilloscope with more than 10M impedance. 4. Clean the object lens by an applicator with neutral detergent when the signal level is low than specified value with the following checks. S Curve Check oscilloscope BD board TP (FEO) TP (VC) Procedure : 1. Connect oscilloscope to test point TP (FEO). 2. Connect between test point TP (FOK) and Ground by lead wire. 3. Turn Power switch on. 4. Put disc (YEDS-18) in and turned Power switch on again and actuate the focus search. (actuate the focus search when disc table is moving in and out.) 5. Check the oscilloscope waveform (S-curve) is symmetrical be- tween A and B. And confirm peak to peak level within 3 1Vp-p. S-curve waveform within 3 1 Vp-p symmetry B A 6. After check, remove the lead wire connected in step 2. Note: Try to measure several times to make sure than the ratio of A : B or B : A is more than 10 : 7. Take sweep time as long as possible and light up the bright- ness to obtain best waveform. Procedure : 1. Connect oscilloscope to test point TP (RF) on BD board. 2. Turned Power switch on. 3. Put disc (YEDS-18) in and playback. 4. Confirm that oscilloscope waveform is clear and check RF sig- nal level is correct or not. Note: Clear RF signal waveform means that the shape “” can be clearly distinguished at the center of the waveform. RF signal waveform VOLT/DIV: 200 mV TIME/DIV: 500 nS level: 1.1 0.3 Vp-p E-F Balance (1 Track Jump) check oscilloscope BD board TP (TEO) TP (VC) Procedure: 1. Connect oscilloscope to test point TP (TEO) on BD board. 2. Turned Power switch on. 3. Put disc (YEDS-18) in to play the number five track. 4. Press the “P (Pause)” button. 5. Check the level B of the oscilloscopes waveform and the A (DC voltage) of the center of the Traverse waveform. Confirm the following: A/B x 100 = less than 7 (%) 1 track jump waveform Center of the waveform B A (DC voitage) Symmetry level : 500 mV 100 mVp-p Adjustment Location: BD BOARD (Conductor Side) CNU102 TP (FOK) TP (RF) 0V IC102 IC101 IC103 TP (TEO) RF Level Check TP (VC) TP (FEO) TP (GND) CNU101 7 Pin No.Pin nameI/ODescription. 1FEOO Focus error amplifier output. Connected internally to the window comparator input for bias adjustment. 2FEIIFocus error input. 3FDFCTICapacitor connection pin for defect time constant. 4FGDIGround this pin through a capacitor for cutting the focus servo high-frequency gain. 5FLBIExternal time constant setting pin for boosting the focus servo low-frequency. 6FE OOFocus drive output. 7FE MIFocus amplifier inverted input. 8SRCHIExternal time constant setting pin for generating focus search waveform. 9TGUIExternal time constant setting pin for switching tracking high-frequency gain. 10TG2IExternal time constant setting pin for switching tracking high-frequency gain. 11FSETIPeak frequency setting pin for focus and tracking phase compensation amplifier. 12TA MITracking amplifier inverted input. 13TA OOTracking drive output. 14SL PISled amplifier non-inverted input. 15SL MISled amplifier inverted input. 16SL OOSled drive output. 17ISETI Connect an external capacitance to set the current which determines the Focus search, Track jump, and Sled kick heights. 18VCCIPositive power supply. 19LOCKIThe sled overrun prevention circuit operates when this pin is Low (No pull-up resistance). 20CLKISerial data transfer clock input from CPU (No pull-up resistance). 21XLTILach input from CPU (No pull-up resistance). 22DATAISerial data input from CPU (No pull-up resistance). 23XRSTIReset input; resets at Low (No pull-up resistance). 24C.OUTOTrack number count signal output. 25SENS1O Outputs FZC, DFCT1, TZC, BALH, TGH, FOH, ATSC, and others according to the command from CPU. 26SENS2O Outputs DFCT2, MIRR, BALL, TGL, FOL,and others according to the command from CPU. 27FOKOFocus OK comparator output. 28CC2IInput for the defect bottom hold output with capacitance coupled. 29CC1O Defect bottom hold output Connected internally to the interruption comparator input. 30CBIConnection pin for defect bottom hold capacitor. 31CPI Connection pin for MIRR hold capacitor MIRR comparator non-inverted input. 32RF IIInput for the RF summing amplifier output with capacitance coupled. 33RF OO RF summing amplifier output Eye-pattern check point. 34RF MI RF summing amplifier inverted input. The RF amplifier gain is determined by the resistance connected between this pin and RFO pin . 35RFTCIExternal time constant setting pin during RF level control. 36LDOAPC amplifier output. 37PDIAPC amplifier input. 38PD1IRF I-V amplifier inverted input. 39PD2IConnect these pins to the photo diode A+C and B+D pins. 40FE BIASI Bias adjustment of focus error amplifier Leave this pin open for automatic adjustment (not used). SECTION 5 DIAGRAMS 5-1. IC PIN FUNCTION IC101 FOCUS/TRACKING/SLED SERVO RF AMP (CXA1992AR) 8 Pin No.Pin nameI/ODescription. 1VDD+5V power supply 2VSSGround 3LMUTOLch “L” detection flog (Not used) 4RMUTORch “L” detection flog (Not used) 5ACDTOTest output (Not used) 6CKOUTOMaster clock divider output (Not used) 7SQCKIClock input for SQSO read out 8SQSOOSerial output for Sub-Q 80bit 9SENSOSENS signal output to CPU 10DATAISerial data input, supplied from CPU 11XLATILatch input, supplied from CPU 12CLOKISerial data transfer clock input, supplied from CPU 13SEINISENS input from IC101 14CNININumbers of track jump counted signal input 15DATOOSerial data output to IC101 16XLTOOSerial data latch output to IC101 17CLKOOSerial data transfer clock output to IC101 18SPOAIMicro computer demodulation interface (Input A) 19SPOBIMicro computer demodulation interface (Input B) 20SPOCIMicro computer demodulation interface (Input C) 21SPODIMicro computer demodulation interface (Input D) 22XLONOMicro computer demodulation interface (Output) (not used) 23FOKIFocus OK input 24VDD+5V power supply 25VSSGround 26MONOOutput to control ON/OFF of spindle motor (Not used) 27MDPOOutput to control spindle motor servo 28MDSOOutput to control spindle motor servo (Not used) 29LOCKOGFS is sampled by 460Hz 30PWMIIInput to control the outside spindle motor 31TES0ITest pin (Connected to ground) 32TES1ITest pin (Connected to ground) 33VPCO2OCharge-pump output (Not used) 34VPCO1OCharge-pump output (Not used) 35VCKIIVCO2 oscillator input (Not used) 36V16MOVCO2 oscillator output (Not used) Pin No.Pin nameI/ODescription. 41FIF I-V and E I-V amplifier inverted input. 42EIConnect these pins to photo diodes F and E. 43EI I-V amplifier E gain adjustment (When not using automatic balance adjustment) (not used). 44VEENegative power supply. 45TEOO Tracking error amplifier output E-F signal is output. 46LPFII Comparator input for balance adjustment (Input from TEO through LPF). 47TEIITracking error input. 48ATSCIWindow comparator input for ATSC detection. 49TZCITrackig zero-cross comparator input. 50TDFCTICapacitor connection pin for defect time constant. 51VCO(VCC + VEE)/2 direct voltage output. 52FZCIFocus zero-cross comparator input. IC103 DIGITAL SIGNAL PROCESSOR (CXD2529Q) 9 Pin No.Pin nameI/ODescription. 37VCTLIVCO2 control voltage input 38PCOOCharge-pump output to master PLL 39FILOOFilter output to master PLL 40FILIIFilter input for master PLL 41AVSSAnalog ground 42CLTVIControl voltage input for VCO 43AVDDAnalog power supply 44RFIEFM signal input 45BIASIAsymmetry circuit constant current input 46ASYIIAsymmetry comparate voltage input 47ASYOOEFM full swing output (“L” =VSS, “H” =VDD) 48ASYEIAsymmetry circuit ON/OFF (“L”=OFF, “H”=ON) 49WDCKOD/A interface Word clock f=2fs (Not used) 50LRCKOD/A interface LR clock output f=Fs 51LRCKIID/A interface LR clock input f=Fs 52PCMDOD/A interface Serial data output 53PCMDIID/A interface Serial data input 54BCKOD/A interface Bit clock output 55BCKIID/A interface Bit clock input 56VSSGround 57VDD+5V power supply 58GTOPNot used 59XUGFNot used 60XPLCKOEFM decoder PLL clock output 61GFSO“H” Playback EFM sync and interpolation protection timming much 62RFCKORead Frame Clock signal output 63C2PONot used 64XRAOFOInternal RAM overflow detection signal output (Not used) 65MNT3Not used 66MNT1Not used 67MNT0Not used 68XTSLNot used 69FSTTO2/3 divider output (Not used) 70C4MO4.2336MHz output(Not used) 71DOUTODigital audio signal output 72EMPHOPlayback disc output in emphasis mode 73EMPHII“H” =Input when de-emphasis ON 74WFCKOWrite Frame Clock signal output 75SCOROSub-code sync output 76SBSOOSub-P through Sub-W serial output 77EXCKIClock input for SBSO read-out 78VSSGround 79VDD+5V power supply 80SYSMISystem mute input (Connected to ground) 81Not used 82AVSSAnalog ground 83AVDDAnalog power supply 84AOUT1OLch analog output 85AIN1ILch opamp input 86LOUT1OLch line output 87AVSSAnalog ground 88XVDDMaster clock power supply 89XTAIIXtal oscillator circuit input 90XTAOOXtal oscillator circuit output 10 Pin No.Pin nameI/ODescription 1GNDGround. 2RMINIRemote control signal input. 3GNDGround. 47NCNot used (Open). 8CLKOSerial clock output. 9SENSEISense signal input from IC103 (CXD2529Q). 10DATAOSerial data output. 11SQCKOSub Q clock output. 12SUBQISub Q data input. 13SENSE2ISense signal input from IC101 (CXA1992AR) 14NCNot used (Open). 15XLTOSerial latch output. 1619NCNot used (Open). 20LD OUTOLoadin motor control. 21LD INOLoadin motor control. 22KEY 0IKey input 0. 23KEY1IKey input 1. 2427NCNot used (Open). 28ADJ/AFADJITest mode terminal. 29IN/OUT SWICD tray IN/OUT switch. 30RSTISystem reset terminal. 31EXTALOSystem oscillator (4.0 MHz). 32XTALISystem oscillator (4.0 MHz). 33VSSGround. 3441NCNot used (Open). 4262S21S1OFL segment signal output. 63671G5GOFL grid signal output. 68NCNot used (Open). 69, 706G,7GOFL grid signal output. 71VFDPPull down voltage ( 30V). 72VDDPower supply (+5V). 73,74GNDGround. 75VDDPower supply (+5V). 76,77NCNot used (Open). 78SCORISub code data request signal input. 79, 80GNDGround. IC501 SYSTEM CONTROL (CXP82612-028Q) Pin No.Pin nameI/ODescription. 91XVSSMaster clock ground 92AVSSAnalog ground 93LOUT2ORch line output 94AIN2IRch opamp input 95AOUT2ORch analog output 96AVDDAnalog power supply 97AVSSAnalog ground 98Not used 99Not used 100XRSTISysyem reset input 24 IC102 BA5941FP + LEVEL SHIFT + 1234567891011121314 2827 LEVEL SHIFT + + MUTE + + LEVEL SHIFT + LEVEL SHIFT + + + 151617181921202226252423 + NC Vcc VccVcc VCC BIAS IN IN1B IN1A IN2B IN2A GND GND MUTE VCC OUT2A OUT2B OUT1A OUT1B IN4B IN4A IN3B IN3A OP OUT OP IN () OP IN (+) GND NC VCC OUT3A OUT3B OUT4A OUT4B IC103 CXD2529Q 3RD-ORDER NOISE SHAPER + + PWMPWM + + VDD VSS LMUT RMUT TES2 CKOUT SQCK SQSO SENS DATA XLAT CLOK SEIN CNIN DATO XLTO CLKO SPOA SPOB SPOC SPOD XLON FOK VDD VSS MON MDP MDS LOCK PWMI 123456789101112131415161718192021222324252627282930 LRCK WDCK ASYE ASYO ASYI BIAS RF AVDD CLTV AVSS FILI FILO PCO VCTL V16M VCKI VPCO1 VPCO2 TES1 TES0 43 42 41 40 39 38 37 36 35 34 33 32 31 50 49 48 47 46 45 44 NC AVSS AVDD AOUT1 AIN1 LOUT1 AVSS XVDD XTAI XTAO XVSS AVSS LOUT2 AIN2 AOUT2 AVDD AVSS NC