Onkyo-TXNR801-avr-sm 电路图 维修手册.pdf

TX-NR801/E SERVICE MANUALSERVICE MANUAL AV RECEIVER MODEL TX-NR801/E Ref. No. 3785 102003 Black, Golden and Silver models BMDD,BMDC120V, AC 60Hz GMWT,GMWR120/220230V, AC 50/60Hz BMPP, SMPP,BMPA,GMPA230240V, AC 50Hz GMGK220V, AC 50Hz DSPA-FO RM LISTENING MODE MEMORYTHXSURROUNDDIRECT / PURE AUDIOSTEREOFM MODEMEMORY ENTER RE TURN SETUP TUNING PRESET SAFETY-RELATED COMPONENT WARNING! COMPONENTS IDENTIFIED BY MARK ON THE SCHEMATIC DIAGRAM AND IN THE PARTS LIST ARE CRITICAL FOR RISK OF FIRE AND ELECTRIC SHOCK. REPLACE THESE COMPONENTS WITH ONKYO PARTS WHOSE PART NUMBERS APPEAR AS SHOWN IN THIS MANUAL. MAKE LEAKAGE-CURRENT OR RESISTANCE MEASUREMENTS TO DETERMINE THAT EXPOSED PARTS ARE ACCEPTABLY INSULATED FROM THE SUPPLY CIRCUIT BEFORE RETURNING THE APPLIANCE TO THE CUSTOMER. 1 RadioFans.CN 收音机爱 好者资料库 TX-NR801/E SPECIFICATIONS AMPLIFIER SECTIONTUNER SECTION FM AM GENERAL Specifications and features are subject to change without notice. Continuous average power output (FTC) (USA and Canadian mod- els): All channels:100 W per channel min. RMS into 8 , 2 channels driven from 20 Hz to 20 kHz with no more than 0.08% total harmonic dis- tortion. 130 W min. RMS into 6 , 2 channels dri ven, 1 kHz with no more than 0.1% total harmonic distortion. Continuous power output (DIN) (European model):135 W at 6 Maximum power output (EIAJ) (Asian model):160 W at 6 Dynamic power output (stereo)2 250 W at 3 2 210 W at 4 2 130 W at 8 Total Harmonic Distortion:0.08% at rated power 0.08% at 1 W output IM Distortion:0.08% at rated power 0.08% at 1 W output Damping factor:60 at 8 Input sensitivity and impedance PHONO:2.5 mV , 50 k LINE (CD, TAPE, DVD, VIDEO 1-5):200 mV , 50 k MULTICHANNEL INPUT (FRONT L/C/R, SUR- ROUND L/R, SURROUND BACK L/R):200 mV , 50 k (SUBWOOFER):36 mV, 50 k COAXIAL 1, 2, 3 (DIGI- TAL):0.5 Vp-p, 75 DVD, VIDEO 1, 2, 3, 4, 5:1 Vp-p, 75 (Composite Video) 1 Vp-p, 75 (S-V ideo, Y signal) 0.28 Vp-p, 75 (S-V ideo, C sig- nal) COMPONENT VIDEO 1, 2:1 Vp-p, 75 (Y) 0.7 Vp-p, 75 (PB/CB, PR/CR) Output level and impedance Rec out (TAPE, VIDEO 1,2): 200 mV , 470 Pre out: 1 V, 470 ZONE 2 OUT :100 mV , 470 VIDEO (VIDEO 1, 2, MONI- TOR OUT , ZONE 2 OUT):1 Vp-p, 75 (Composite Video) S-VIDEO (VIDEO 1, 2, MONIT OR OUT):1 Vp-p, 75 (S-V ideo, Y signal) 0.28 Vp-p, 75 (S-V ideo, C sig- nal) COMPONENT VIDEO OUT : 1 Vp-p, 75 (Y) 0.7 Vp-p, 75 (PB/CB, PR/CR) Phono overload:120 mV RMS at 1 kHz, 0.5% T.H.D. Frequency response:10 Hz to 100 kHz: +1/-3 dB (CD in Direct mode) RIAA deviation:20 Hz to 20 kHz: 0.8 dB Tone Control Bass:10 dB at 50 Hz Treble:10 dB at 20,000 Hz Signal-to-noise ratio (direct) PHONO: Line: 80 dB (IHF A, 5 mV input) 110 dB (IHF A, 0.5 V input) Ethernet port:100BASE-TX Supported audio file format:MP3, WMA, WAV (non-compres- sion, sampling rates of 32 kHz, 44.1 kHz, and 48 kHz supported) Tuning range USA 1IN LOW; 2IN ( ) TA1270BF(PAL/NTSC Video Chroma and Sync. Processing system for PIP/POP/PAP) 49 TX-NR801/E IC BLOCK DIAGRAMS AND DESCRIPTIONS CHIP SELECT 10BIT SHIFT REGISTER GAIN SELECT DECODER TIMING GENERATOR L/R & BAND SELECT DECODER L1L11 R1R11 RESISTOR NETWORK & ANALOG SW LATCH LATCH RESISTOR NETWORK & ANALOG SW TEST CIRCUIT Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above CS CLK DI fR1 fR2 fR3 fR4 fR5 fR6 fR7 fR8 fR9 fR10 fR11 TEST1 TEST2 VDD VCC VSS VEE fL1 fL2 fL3 fL4 fL5 fL6 fL7 fL8 fL9 fL10 fL11 IN1LIN2LIN1R IN2R Q4400,Q4401 NJU7306G(Electric Volume) VDD IN1L IN2L NC fL11 fL10 fL9 fL8 fL7 fL6 fL5 fL4 fL3 fL2 fL1 TEST1 TEST2 VEE NC CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC IN1R IN2R NC fR11 fR10 fR9 fR8 fR7 fR6 fR5 fR4 fR3 fR2 fR1 NC Vss CLK DI Vcc VIN1+ NFB1 MUTE1 VIN2+ NFB2 -VCC1 VIN3+ NFB3 +VCC VOUT1 GND VOUT2 DR CTL VOUT3 MUTE2 -VCC2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 6dBDR 6dBDR 6dBDR Q2801 LA7106MFP(75 ohm video driver) 50 TX-NR901 IC BLOCK DIAGRAMS AND DESCRIPTIONS CONTROL INPUT LOGIC PROGRAM/ERASE HIGH VOLTAGE WRITE STATE MACHINE (WSM) STATE REGISTER MX29LV320AT/B FLASH ARRAY X-DECODER ADDRESS LATCH AND BUFFER Y-PASS GATE Y-DECODER ARRAY SOURCE HV COMMAND DATA DECODER COMMAND DATA LATCH I/O BUFFER PGM DATA HV PROGRAM DATA LATCH SENSE AMPLIFIER Q0-Q15/A-1 A0A20 WE OE WP RESET BYTE BLOCK DIAGRAM BLOCK DIAGRAM PIN DESCRIPTION SYMBOLPIN NAME A0A20Address Input Q0Q14Data Input/Output CEChip Enable Input WEWrite Enable Input RESETHardware Reset Pin/Sector Protect Unlock OEOutput Enable Input VCCPower Supply Pin (+5V) GNDGround Pin Q604 MX29LV320AT/B(32Mbit CMOS Flash memory) Q15/A-1 BYTE RY/BY WP/ACCHardware Write Protect/Acceleration Pin Q15:Data Input/Output,word mode A-1:LSB Address Input,byte mode Word/Byte Selection Pin Read/Busy output MX29LV320AT/B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET NC WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND CE A0 51 TX-NR801/E IC BLOCK DIAGRAMS AND DESCRIPTIONS Q7502 M66005-0001AFP(FL tube drive IC) CS SCK SDATA RESET Xin Xout Vcc1Vcc2 SERIAL RECEIVE CIRCUIT DISPLAY CODE RAM (8 bits16) CODE/ COMMAND CONTROL CIRCUIT INDICATOR CONTROL REGISTER CLOCK GENERATOR CIRCUIT DISPLAY CONTROLLER RAM write code selector CGROM (35 bits 160) CGRAM (35 bits 16) SEGMENT OUTPUT CIRCUIT DIGIT OUTPUT CIRCUIT SEG36 SEG28 SEG27 SEG01 P1 P0 VssVp DECODERDECODER DIG16/SEG40 DIG13/SEG37 DIG12 DIG01 1 12 61 64 22 20 21 13 16 15 14 1960 59 33 32 31 23 18 17 SEGMENT/DIGIT SELECT/OUTPUT CIRCUIT Q2752/Q2753 MM1093(4fsc clock generator) 4fsc VCO DIVIDER (1/4) SYNC SEP BGP GEN APC2 1st BPA 2nd BPA fsc VCXO ACC DET 9 10 11 12 13 14 15 16 OSCILLATOR R Vcc1 Vcc2 OSCILLATOR C APC2 FILTER 4fsc OUTPUT BURST GATE FILTER COMPOSITE INPUT 8 7 6 5 4 3 2 1 NC fsc OUTPUT GND2 GND1 XTAL APC 1 FILTER ACC FILTER CHROMA INPUT APC1 52 CS SIN SCLK RST CTR-A CTR-B NSDET SDET VDD1 VDD2 VSS SYNCDET VCOIN VCOOUT FC AMPIN AMPOUT PDOUT SYSIN SEPC SERIAL PARALLEL CONVERSION A F C CIRCUIT SYNCHRO- NIZING SEPARATION COMPOSITE SYNCHRONIZING SEPARATION CIRCUIT INDICATOR RAM DECODER ROM SHIFT REGISTER HSYN OUT VSYN OUT XTAL IN1 XTAL IN2 XTAL OUT1 XTAL OUT2 CVCR CVIN CVOUT ON/OFF INVERSION CONTROL CIRCUIT 8 BITS LATCH AND COMMAND DECODER COMPOSITE SYNCHRO- NIZING SIGNAL CONTROL SYNCHRO- NIZING DISCRIMI- NATION HORIZONTAL CHARACTER SIZE REGISTER VERTICAL CHARACTER SIZE REGISTER VERTICAL INDICATION POSITION REGISTER HORIZONTAL INDICATION POSITION REGISTER CHARACTER OUTPUT CONTROL BACKGROUND CONTROL VIDEO OUTPUT CONTROL SYNCHRONIZING SIGNAL GENERATOR TIMING GENERATOR CHARACTER CONTROL COUNTER LINE CONTROL COUNTER HORIZONTAL INDICATION POSITION DETECTOR VERTICAL INDICATION POSITION DETECTOR ON/OFF INVERSION CONTROL REGISTER INDICATOR CONTROL REGISTER RAM WRITE ADDRESS COUNTER DECODER VERTICAL DOT COUNTER HORIZONTAL DOT COUNTER VERTICAL SIZE COUNTER HORIZONTAL SIZE COUNTER FONT No. SymbolDescriptionNo.SymbolDescription 1VSSGround terminal16CVOUTComposite video output terminal 2XTALIN1 Crystal oscillator connection terminals for. 17VDD2Power supply terminal for composite video signal 3XTALOUT1internal synchronizing signal generator18CVINComposite video signal input terminal 4HSYNCOUTHorizontal synchronizing signal output terminal19CVCRCromatic signal input term,inal 5XTALIN2 Crystal oscillator connection terminals for. 20SYNCINVideo signal input terminal for internal synchronizing separation circuit 6XTALOUT2internal synchronizing signal generator21SEPCBias output pin for internal synchronizing separation circuit 7VSYNCOUT Vertical synchronizing signal output terminal22VSSGround terminal 8CSChip enable input terminal23PDOUTPower supply output terminal for AFC circuit 9SINSerial data input terminal24AMPIN Filter connection terminals 10SCLKClock input terminal for serial data 25AMPOUT 11CTR-A/SW1 Video control output terminal26FCPower supply output terminal 12CTR-B/SW2 Video control output terminal27VCOIN LC resonator connection terminals for VCO 13NSDET/SW3 Selection pin for PAL or NTSC28VCOOUT 14SDET/SW4Signal detection terminal29SYNCDETExternal synchronizing signal discrimination output terminal 15RSTSystem reset input terminal30VDD1Power supply terminal Pin 1114: The output signal changes according to the contents of a microprocessor. TX-NR801/E IC BLOCK DIAGRAMS AND DESCRIPTIONS Q2001 LC74761M-9848(On-screen and controller) 53 TX-NR801/E IC BLOCK DIAGRAMS AND DESCRIPTIONS G1 A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Vcc G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Z Z H L X :Dont care Z :High impedance G1 H X L L G2 X H L L An X X H L OUTPUT INPUTS Q7100 TC74VHC541FT(Octal bus buffer) CLR L H L H H H PR H L L H H H D X X X L H X CK X X X Q L H H L H Qn Q H L H H L Qn CLEAR PRESET NO CHANGE INPUTSOUTPUTSFUNCTION X: Dont care Q701,Q751 TC74VHC74FT(Dual D-FF with preset and clear) 1 2 3 4 5 6 7 1CLR 1D 1CK 1PR 1Q 1Q GND 14 13 12 11 10 9 8 Vcc 2CLR 2D 2CK 2PR 2Q 2Q CK D Q Q CK D Q Q 1A 1B 1Y 2A 2B 2Y GND Vcc 4B 4A 4Y 3B 3A 3Y 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Q121 TC74VHCT00A(2-input NAND gate) IN B IN A GND 1 2 3 5 4 Vcc OUT Y A L L H H B L H L H Y H L L L Q610 TC7S02FU(2-input NOR gate) A L L H H B L H L H Y H H H L 1A 3Y 2A GND 1 2 3 4 8 7 6 5 Vcc 1Y 3A 2Y Q609 TC7W14FU (Schmidt Inverter) 54 TX-NR801/E IC BLOCK DIAGRAMS AND DESCRIPTIONS 1A 1Y 2A 2Y 3A 3Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Vcc 6A 6Y 5A 5Y 4A 4Y (TOP VIEW) A L H Y L H Truth table Q7102 TC74HCT7007AF(Hex buffer) Q190 TC74VHC157FT(Quad 2-channel Multiplexer) Q120 TC74VHC4040FT(12-stage ripple-carry binary counter) SELECT 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Vcc ST 4A 4B 4Y 3A 3B 3Y (TOP VIEW) INPUTS OUTPUT ST H L L L L SELECT X L L H H A X L H X X B X X X L H L L H L H X:Dont care A B Y A B Y S Y G A B Y A B 1A 1B 2A 2B 3A 3B 4A 4B (2) (3) (5) (6) (11) (10) (14) (13) 1Y 2Y 3Y 4Y (4) (7) (9) (12) ST SELECT (15) (1) 1 1 MUX 1 2 3 4 5 6 7 8 Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND 16 15 14 13 12 11 10 9 Vcc Q11 Q10 Q8 Q9 CLR CK Q1 CK X CLR H L L OUTPUT All L No change Next condition X: Dont care Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 (9) (7) (6) (5) (3) (2) (4) (13) (12) (14) (15) (1) RCTR 12 0 11 CT=0 +CT CLR CK (11) (10) 55 TX-NR801/E IC BLOCK DIAGRAMS AND DESCRIPTIONS 1 2 3 4 5 6 7 8 4 6 COM 7 5 INH VEE GND 16 15 14 13 12 11 10 9 Vcc 2 1 0 3 A B C Q2101 74HC4051AF(8-channel analog multiplexer/demultiplexer) CONTROL INPUTS INHIBIT L L L L L L L L H C L L L L H H H H X B L L H H L L H H X A L H L H L K L H X ON 0 1 2 3 4 5 6 7 NONE OUTPUT 1A 1Y 2A 2Y 3A 3Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Vcc 6A 6Y 5A 5Y 4A 4Y (TOP VIEW) A L H Y H L Truth table Q130 74HCU04F(Hex Inverters) Truth table 56 TX-NR801/E FL TUBE VIEW HNA-16MM40T AC-3 RF IEEE1394 AACUltra2 Select2 14G 13G 12G 11G 10G 9G 8G 7G 6G 5G 4G 3G 2G 1G 15G 16G(Left) (Right) (Center) 1-1 1-2 1-3 1-4 1-5 1-6 1-7 3-1 3-2 3-3 3-4 3-5 3-6 3-7 4-1 4-2 4-3 4-4 4-5 4-6 4-7 5-1 5-2 5-3 5-4 5-5 5-6 5-7 2-1 2-2 2-3 2-4 2-5 2-6 2-7 8 a b c c d e f g h i j k l m n o p q (Left) (Right) (1) (2) (3) P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 16G15G14G1G 16G15G14G1G P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 1-1 2-1 3-1 4-1 5-1 1-2 2-2 3-2 4-2 5-2 1-3 2-3 3-3 4-3 5-3 1-4 2-4 a b c d e f g h 3-4 4-4 5-4 1-5 2-5 3-5 4-5 5-5 1-6 2-6 3-6 4-6 5-6 1-7 2-7 3-7 4-7 5-7 8 i j k l m n o p q - - - - - - - - - AC-3 RF IEEE1394 AAC Ultra2 Select2 (Left) (Right) (Center) (Left) (Right) (1) (2) (3) (Center) (Right) (Center) - 14G1G 15G 57 TX-NR801/E IC BLOCK DIAGRAMS AND DESCRIPTIONS CS8900A(Ethernet Controller) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol AVSS0 ELCS EECS EESK EEDataOut EEDataiN CHIPSEL DVSS1 DVDD1 DVSS1A DMARQ2 DMACK2 DMARQ1 DMACK1 DMARQ0 DMACK0 CSOUT SD15 SD14 SD13 SD12 DVDD2 DVSS2 SD11 SD10 SD09 SD08 MEMW MEMR INTRQ2 INTRQ1 INTRQ0 IOCS16 MEMCS16 INTRQ3 SBHE SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 REFRESH SA12 Description Analog ground pin External logic chip select pullup pin EEPROM chip select output pin EEPROM serial clock pin EEPROM data output pin EEPROM data input pin Chip select pin Digital ground pin Digital power source pin Digital ground pin DMA(Direct Memory Access) request output pin DMA acknowledge input pin DMA request output pin DMA acknowledge input pin DMA request output pin DMA acknowledge input pin Chip select output pin for external boot EROM System data bus output pin System data bus output pin System data bus output pin System data bus output pin Digital power source pin Digital ground pin System data bus output pin System data bus output pin System data bus output pin System data bus output pin Memory write input pin Memory read input pin Interrupt request output pin Interrupt request output pin Interrupt request output pin I/O chip select 16-bit output pin Memory chip select 16-bit output pin Interrupt request output pin System bus high enable input pin System address bus input pin System address bus input pin System address bus input pin System address bus input pin System address bus input pin System address bus input pin System address bus input pin System address bus input pin System address bus input pin System address bus input pin System address bus input pin System address bus input pin Refresh input pin System address bus input pin Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol SA13 SA14 SA15 SA16 DVSS3 DVDD3 DVSS3A SA17 SA18 SA19 IOR IOW AEN IOCHRDY SD0 SD1 SD2 SD3 DVDD4 DVSS4 SD4 SD5 SD6 SD7 RESET TEST SLEEP BSTATUS or HC1 DI+ DI- CI+ CI- DO+ DO- AVDD2 AVSS2 TXD+ TXD- AVSS1 AVDD1 RXD+ RXD- RES AVSS3 AVDD3 AVSS4 XTAL1 XTAL2 LINKLED or HC0 LANLED Description System address bus input pin System address bus input pin System address bus input pin System address bus input pin Digital ground pin Digital power source pin Digital ground pin System address bus input pin System address bus input pin System address bus input pin I/O read input pin I/O write input pin Address enable input pin I/O channel ready output pin System data bus output pin System data bus output pin System data bus output pin System data bus output pin Digital power source pin Digital ground pin System data bus output pin System data bus output pin System data bus output pin System data bus output pin Reset input Test enable input pin Hardware sleep input pin Bus status or host controlled output pin AUI(Attachment Unit Interface) dat