Marantz-CC4003-cd-sm 电路图 维修手册.pdf

CC4003 Please use this service manual with referring to the user guide ( D.F.U. ) without fail. Service Manual CC4003 5 Disc CD Changer CC4003 /FB/N1B/U1B Part no. 90M21DW855020 First Issue 2009.10 TABLE OF CONTENTS SECTION PAGE 1. TECHNICAL SPECIFICATIONS .1 2. SERVICE HINTS AND TOOLS .2 3. WARNING AND LASER SAFETY INSTRUCTIONS .3 4. CAUTION .4 5. TAKING THE DISC OUT OF EMERGENCY .6 6. SERVICE MODE .7 7. UPDATE DSP FIRMWARE PROCEDURE .8 8. WIRING DIAGRAM .9 9. BLOCK DIAGRAM .11 10. SCHEMATIC DIAGRAM .13 11. PARTS LOCATION .17 12. EXPLODED VIEW AND PARTS LIST .27 13. MICROPROCESSOR AND IC DATA .31 14. ELECTRICAL PARTS LIST .41 15. ABOUT REPLACE THE MICROPROCESSOR WITH A NEW ONE.52 X0412V01DM/DG0910 Copyright 2009 D when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Or this pin inputs when LKIN = 1. Spindle motor servo control output. Disk innermost detection signal input. I/O digital GND. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. I/O digital power supply. Analog power supply. Analog GND. E signal input. F signal input. Tracking error signal input to DSSP block. Tracking error signal output from RF amplifier block. Focus error signal input to DSSP block. Focus error signal output from RF amplifier block. Center voltage output from RF amplifier block. Center voltage input to DSSP block by command switch. A signal input. B signal input. C signal input. D signal input. Analog power supply. RFDC signal output. RFDC signal input to DSSP block by command switch. Reference voltage pin for PD. RFAC summing amplifier output. Power supply 1, 0 1, 0 1, 0 1, 0 1, Z, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 Analog Digital I/O = 3.3V Internal = 2.5V A/D 3.3V RFamp 3.3V 33 5 CXD3059AR Pin No. SymbolI/ODescription 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 EQ_IN LD PD NC RFC AVSS4 RFACO RFACI AVDD3 BIAS ASYI ASYO VPCO VCTL AVSS3 CLTV FILO FILI PCO AVDD5 DDVROUT DDVRSEN AVSS5 DDCR NC BCKI PCMDI LRCKl LRCK VSS PCMD BCK VDD EMPH EMPHI I O I I O I I I O O I I O I O O I I I I I O O O O I Equalizer circuit input. APC amplifier output. APC amplifier input. Equalizer cut-off frequency adjustment pin. Analog GND. RFAC signal output. RFAC signal input or EFM signal input. Analog power supply. Asymmetry circuit constant current input. Asymmetry comparator voltage input. EFM full-swing output. (Low = VSS, High = VDD) Wide-band EFM PLL charge pump output. Wide-band EFM PLL VCO2 control voltage input. Analog GND. Multiplier VCO1 control voltage input. Master PLL (slave = digital PLL) filter output. Master PLL filter input. Master PLL charge pump output. Analog power supply. DC/DC converter output. Leave open when not using. DC/DC converter output voltage monitor pin. Connect to analog power supply when not using. Analog GND. Test pin. Normally GND. D/A interface bit clock input. D/A interface serial data input. (2s COMP, MSB first) D/A interface LR clock input. D/A interface LR clock output. f = Fs Internal digital GND. D/A interface serial data output. (2s COMP, MSB first) D/A interface bit clock output. Internal digital power supply. High when the playback disc has emphasis, low it has not. High when de-emphasis is ON, low when input OFF. Power supply 1, 0 1, Z, 0 Analog 1, Z, 0 1, 0 1, 0 1, 0 1, 0 RFamp 3.3V ASYM 3.3V DC/DC 3.3V Digital I/O = 3.3V Internal = 2.5V 34 6 CXD3059AR Pin No. SymbolI/ODescription 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 IOVDD2 DOUT TEST TES1 IOVss2 NC XVSS XTAO XTAI XVDD AVDD1 AOUT1 VREFL AVSS1 AVSS2 VREFR AOUT2 AVDD2 NC IOVDD0 RMUT LMUT NC XTSL IOVSS0 XTACN SQSO SQCK SBSO EXCK XRST SYSM DATA VSS XLAT O I I O I O O O O O O I I O I O I I I I I I/O digital power supply. Digital Out output. Test pin. Normally GND. Test pin. Normally GND. I/O digital GND. Master clock GND. Crystal oscillation circuit output. Crystal oscillation circuit input. Master clock power supply. Analog power supply. Lch analog output. Lch reference voltage. Analog GND. Analog GND. Rch reference voltage. Rch analog output. Analog power supply. I/O digital power supply. Rch 0 detection flag. Lch 0 detection flag. Crystal selection input. Low when the crystal is 16.9344MHz; high when the crystal is 33.8688MHz. I/O digital GND. Oscillation circuit control. Self-oscillation when high, oscillation stop when low. Subcode Q 80-bit and PCM peak and level data output. CD TEXT data output. SQSO readout clock input. Subcode P to W serial output. SBSO readout clock input. System reset. Reset when low. Mute input. Muted when high. Serial data input from CPU. Internal digital GND. Latch input from CPU. The serial data is latched at the falling edge. Power supply 1, 0 1, 0 1, 0 1, 0 1, 0 Xtal 2.5V Digital I/O = 3.3V Internal = 2.5V Lch 3.3V Rch 3.3V Digital I/O = 3.3V Internal = 2.5V 35 7 CXD3059AR Pin No. SymbolI/ODescription 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 CLOK VDD SENS SCLK ATSK WFCK XUGF XPCK GFS C2PO SCOR VDD C4M WDCK COUT NC I O I I/O O O O O O O O O I/O Serial data transfer clock input from CPU. Internal digital power supply. SENS output to CPU. SENS serial data readout clock input. Anti-shock input/output. WFCK output. XUGF output. Output MNT0, RFCK, SOUT by command switch. XPCK output. Output MNT1, SOCK by command switch. GFS output. Output MNT2, XROF, XOLT by command switch. C2PO output. Output MNT3, GTOP by command switch. High output when the subcode sync, S0 or S1, is detected. Internal digital power supply. 4.2336MHz output. 1/4 frequency-division output of the V16M in CAV-W mode and variable pitch mode. Word clock output. f = 2Fs. GRSCOR output by command switch. Track number count signal input/output. Power supply 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 Digital I/O = 3.3V Internal = 2.5V Notes) PCMD is a MSB first, twos complement output. GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection. XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. The GFS signal goes high when the frame sync and the insertion protection timing match. RFCK is derived from the crystal accuracy, and has a cycle of 136s. C2PO represents the data error status. XROF is generated when the 32K RAM exceeds the 28 frame jitter margin. C4M is a 4.2336MHz output that changes in CAV-W mode and variable pitch mode. FSTO is the 2/3 frequency-division output of the XTAI pin. SOUT is the serial data output inside the servo block. SOCK is the serial data readout clock output inside the servo block. XOLT is the serial data latch output inside the servo block. IC104 : SP232ACP SP231ADS/01SP231A Enhanced RS-232 Line Drivers/Receivers Copyright 2000 Sipex Corporation 3 PERFORMANCE CURVES -55-400257085125 Temperature (C) 0 5 10 15 20 25 30 VCC = 6V VCC = 5V VCC = 4V VCC = 3V ICC (mA) 4.54.755.05.255.5 VCC (Volts) 6.8 7.4 7.6 7.8 8.0 8.2 8.4 Load current = 0mA TA = 25C VOH (Volts) 7.0 7.2 05101520 Load Current (mA) 0 6 8 10 12 V+ (Volts) 2 4 VCC = 5V VCC = 4V VCC = 6V 2530354002468101214 Load Current (mA) V Voltage (Volts) -3 -4 -5 -6 -7 -8 -9 -10 -11 VCC = 6V VCC = 5V VCC = 4V PINOUT V+ VCC GND T1 OUT R1 IN R1 OUT T1 IN C+ C- V- T2 OUT R2 IN R2 OUT T2 IN SP231A 1 2 3 4 5 6 7 14 13 12 11 10 9 8 14-Pin Plastic DIP V+ VCC GND T1 OUT R1 IN R1 OUT T1 IN NC C+ C- V- T2 OUT R2 IN R2 OUT T2 IN NC 16-Pin SOIC SP231A 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 R OUT R IN T OUT V- C - C + V+ C - V- C + 2 1 2 T IN T IN R OUT R IN T OUT GND V C + GND C - 1 2 2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 1 1 1 CC 1 2 2 2 2 SP233ACP 20-PIN PLASTIC DIP R OUT R IN T OUT V- C - C + C C + C + C 2 1 2 T IN T IN R OUT R IN T OUT GND V V+ GND V 1 2 2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 1 1 1 CC 2 2 2 2 SP233ACT 1 20-PIN SOIC V GND T OUT R IN R OUT T IN T IN R OUT CC 1 2 C + V+ C - C + C - V- T OUT R IN 1 1 1 SP232A 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 2 2 2 1 2 SHUTDOWN V GND T OUT R IN R OUT T IN T IN R OUT EN C + V+ C - C + C - V- T OUT R IN 2 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 1 1CC 22 SP312A 2 1 2 2 1 1 1 ON/OFF V GND T OUT R IN R OUT T IN T IN R OUT NC C + V+ C - C + C - V- T OUT R IN 2 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 1 1CC 22 SP310A 2 1 2 2 1 1 1 SP231ADS/01SP231A Enhanced RS-232 Line Drivers/Receivers Copyright 2000 Sipex Corporation 5 R2 98 R INR OUT 2 R1 1213 R INR OUT 1 T2 107 T IN 2 T OUT 2 T1 1114 T IN 1 T OUT 1 15GND 400k 400k TTL/CMOS INPUTS RS-232 OUTPUTS 3 1 C + C - 1 1 6 16 VCC V+ + + 0.1 F 6.3V +5V to +10V Voltage Doubler +5V INPUT 2 V- TTL/CMOS OUTPUTS RS-232 INPUTS 2 1 5k 0.1 F 16V 5k 5 4 C + C - 2 2+ 0.1 F 16V +10V to -10V Voltage Inverter 0.1 F 6.3V 10 F 6.3V SP232A + + * *The negative terminal of the V+ storage capacitor can be tied to either VCC or GND. Connecting the capacitor to VCC (+5V) is recommended. Figure 3. Typical Circuits using the SP231A and 232A. R2 65 R INR OUT 2 R1 910 R INR OUT 1 T2 74 T IN 2 T OUT 2 T1 811 T IN 1 T OUT 1 12GND 400k 400k TTL/CMOS INPUTS RS-232 OUTPUTS 2 1 C + C - 1 1 3 13 VCC V+ + + 0.1 F 6.3V +5V INPUT 14 V- TTL/CMOS OUTPUTS RS-232 INPUTS 2 1 5k 0.1 F 16V 5k +12V to -12V Voltage Inverter SP231A V+ (+8.5V to +13.2V) Receivers The receivers convert RS-232 input signals to inverted TTL signals. Since the input is usually from a transmission line, where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 500mV. This ensures that the receiver is virtually immune to noisy transmission lines. The input thresholds are 0.8V minimum and 2.4V maximum, again well within the 3V RS-232 requirements. The receiver inputs are also protected against voltages up to 30V. Should an input be left unconnected, a 5kOhm pulldown resistor to ground will commit the output of the receiver to a high state. In actual system applications, it is quite possible for signals to be applied to the receiver inputs before power is applied to the receiver circuitry. This occurs, for example, when a PC user attempts to print, only to realize the printer wasnt turned on. In this case an RS-232 signal from the PC will appear on the receiver input at the printer. When the printer power is turned on, the receiver will operate normally. All of these enhanced devices are fully protected. Charge Pump The charge pump section of the these devices allows the circuit to operate from a single +5V 10% power supply by generating the required operating voltages internal to the devices. The charge pump consists of two sections 1) a voltage doubler and 2) a voltage inverter. As shown in Figure 1, an internal oscillator trig- gers the charge accumulation and voltage inver- sion. The voltage doubler momentarily stores a charge on capacitor C1 equal to Vcc, referenced to ground. During the next transition of the oscillator this charge is boot-strapped to transfer charge to capacitor C3. The voltage across C3 is now from Vcc to V+. In the inverter section (Figure 2), the voltage across C3 is transferred to C2 forcing a range of 0V to V+ across C2. Boot-strapping of C2 will then transfer charge to C4 to genrate V-. One of the significant enhancements over previous products of this type is that the values of the capacitors are no longer critical and have been decreased in size considerably to 0.1F. Because the charge pump runs at a much higher frequency, the 0.1F capacitors are sufficient to transfer and sustain charges to the two transmitters. APPLICATION HINTS Protection From Shorts to 15V The driver outputs are protected against shorts to ground, other driver outputs, and V+ or V-. If the possibility exists that the outputs could be inadvertently connected to voltages higher than 15V, then it is recommended that external protection be provided. For protection against voltages exceeding 15V, two back-to-back zener diodes connected from each output to ground will clamp the outputs to an acceptable voltage level. 36 IC105 : BA6392FPE2 325 Optical disc ICsBA6392FP Block diagram 326 Optical disc ICsBA6392FP Pin descriptions 37 IC112 : CS4392 Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. 1 CopyrightCirrus Logic, Inc. 2002 (All Rights Reserved) CS4392 24-Bit, 192 kHz Stereo DAC with Volume Control Features Complete Stereo DAC System: Interpolation, D/A, Output Analog Filtering 114 dB Dynamic Range 100 dB THD+N Up to 192kHz Sample Rates Direct Stream Digital Mode Low Clock Jitter Sensitivity Single +5 V Power Supply Selectable Digital Filters Fast and Slow roll-off Volume Control with Soft Ramp 1 dB Step Size Zero Crossing Click-Free Transitions Direct Interface with 5 V to 1.8 V Logic ATAPI mixing functions Pin compatible with the CS4391 Description The CS4392 is a complete stereo digital-to-analog sys- tem including digital interpolation, fifth-order delta-sigma digital-to-analog conversion, digital de-emphasis, vol- ume control, channel mixing and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching erro