AD9910.PDF

1 GSPS 14-Bit, 3.3V CMOS Direct Digital Synthesizer Preliminary Technical Data AD9910 Rev. PrD Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 2006 Analog Devices, Inc. All rights reserved. FEATURES 1GSPS internal clock speed (up to 400MHz analog out) Integrated 1GSPS 14-bit DAC 32-bit tuning word Phase noise 123 dBc/Hz 1 kHz offset (400Mhz carrier) Excellent dynamic performance 80 dB narrowband SFDR Serial I/O control Automatic linear and nonlinear frequency sweeping capability 8 frequency/phase offset profiles 1.8V frequency, phase, and amplitude. The ability to generate a time-dependent amplitude, phase, or frequency sig- nal enables modulation of any one of the parameters controlling the DDS carrier signal. In addition, a polar modulation format is also available, in which each RAM sample is partitioned into a magnitude and phase component: 16 bits phase allocated to phase and 14 bits allocated to magnitude. NOTE: When the OSK function is enabled, its amplitude data overrides any RAM data that is destined for the DDS amplitude control parameter. Figure 5: RAM modulation mode LINEAR RAMP MODULATION MODE In linear ramp modulation mode (Figure 6), the modulated DDS signal control parameter is supplied directly from Linear Ramp Generator. The ramp generation parameters are con- trolled via the serial I/O port. The ramp generation parameters allow the user to control both the rising and falling slopes of the ramp. The upper and lower boundaries of the ramp, the step size and step rate of the rising portion of the ramp, and the step size and step rate of the falling portion of the ramp are all programmable. The ramp is digitally generated with 32-bit output resolution. The 32-bit output of the Linear Ramp Generator can be pro- grammed to represent frequency, phase, or amplitude. When programmed to represent frequency all 32 bits are used. How- ever, when programmed to represent phase or amplitude, only the 16 MSBs or 14 MSB, respectively, are used. The ramp direction (rising/falling) is controlled externally by the LSCTL pin. An additional pin (LSHOLD) allows the user to freeze the ramp generator at its present state. NOTE: When the OSK function is enabled, its amplitude data overrides any Linear Ramp data that is destined for the DDS am- plitude control parameter. PRELIMINARY TECHNICAL DATA AD9910 Rev. PrD| Page 12 of 13 Figure 6: Linear ramp modulation mode PARALLEL DATA PORT MODULATION MODE In parallel data port modulation mode (Figure 7) the modu- lated DDS signal control parameter(s) are supplied directly from the 18-bit parallel data port. The data port is partitioned into two sections. The 16 MSBs make up a 16-bit data word and the 2 LSBs make up a 2-bit destination word. The destination word defines how the 16-bit data word is applied to the DDS signal control parameters. Table 2 defines the relationship between the destination bits, the partitioning of the 16-bit data word and the destination of the data (in terms of the DDS signal control parameters). NOTE: When the OSK function is enabled, its amplitude data overrides any parallel port data that is destined for the DDS am- plitude control parameter. The sample rate of the parallel data port is of the DAC sample rate. The AD9910 generates the PDCLK signal, which is a clock signal that runs at of the DAC sample rate and serves as a data clock. Each rising edge of PDCLK is used to latch the 18 bits of user-supplied data into the data port. The AD9910 also accepts a user generated TxEn signal that acts as a gate for the user supplied data. When TxEn is logic 0 the device ignores the data supplied to the port. However, inter- nally, the 16-bit data words are either forced to logic zeros or held at their last state when TxEn transitions from a logic 1 to a logic 0. The treatment of the 16-bit data words when TxEn is logic 0 is controlled by a bit in the programming registers. The destination bits, on the other hand, always retain their last state when TxEn transitions to a logic 0. When the destination bits indicate that the data word is des- tined as a DDS frequency parameter, there is an additional con- sideration. Recall that the DDS frequency parameter is a 32-bit word. However, the data word is only 16 bits, which means that the 16-bit data word must somehow be properly aligned with the 32-bit frequency parameter. This is accomplished by means of 4-bit FM Gain word in the programming registers. The FM Gain word allows the user to apply a weighting factor to the 16- bit data word. The default value of the FM Gain word is 0. In the default state, the data word and the DDS frequency parameter are LSB aligned. Each increment in the value of the FM Gain word shifts the 16-bit data word to the left relative to the DDS fre- PRELIMINARY TECHNICAL DATA AD9910 Rev. PrD| Page 13 of 13 PR06464-0-10/06(PrD) quency parameter, thereby increasing its affect on the DDS fre- quency by a factor of 2. The FM Gain word effectively controls the maximum frequency range spanned by the data word. Table 2: Parallel port destination bits Destination Bits Data Word Parti- tioning DDS Signal Control Parameter Remarks 00 14-bit amplitude parame- ter (unsigned integer) Amplitude scales from 0 to 1-2-14. are ignored. 01 16-bit phase parameter (unsigned integer) Phase offset ranges from 0 to 2(1-2-16) radians. 10 32-bit frequency parame- ter (unsigned integer) The alignment of 16-bit data word with the 32-bit frequency pa- rameter is controlled by a 4-bit FM Gain word in the programming registers. 11 8 bits amplitude (un- signed integer) 8 bits phase (unsigned integer) The MSB of the data word amplitude aligns with the MSB of the DDS s 14-bit amplitude parameter. The 6 LSBs of the DDS s ampli- tude parameter are assigned from bits of the ASF register. The resulting 14-bit word scales the amplitude from 0 to 1-2-14. The MSB of the data word phase aligns with the MSB of the DDS s 16-bit phase parameter. The 8 LSBs of the DDS s phase parameter are assigned from bits of the POW register. The resulting 16- bit word offsets the phase from 0 to 2(1-2-16) radians. Figure 7: Parallel data port modulation mode