Denon-AVR3313-avr-sm维修电路图 手册.pdf

D this pad must be robustly connected to GND. RadioFans.CN 193 W9864G6JH-6 (HDMI : IC409) W9864G2IH Publication Release Date: Aug. 28, 2009 - 4 - Revision A03 4. PIN CONFIGURATION RadioFans.CN 194 W9864G6JH-6 Block diagram W9864G2IH Publication Release Date: Aug. 28, 2009 - 6 - Revision A03 6. BLOCK DIAGRAM DQ0 DQ31 DQM03 CLK CKE A10 CLOCK BUFFER COMMAND DECODER ADDRESS BUFFER REFRESH COUNTER COLUMN COUNTER CONTROL SIGNAL GENERATOR MODE REGISTER COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #2 COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #0 COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #3 DATA CONTROL CIRCUIT DQ BUFFER COLUMN DECODER SENSE AMPLIFIER CELL ARRAY BANK #1 ROW DECODER ROW DECODER ROW DECODERROW DECODER A0 A9 BS0 BS1 CS RAS CAS WE RadioFans.CN 195 W9864G6JH-6 Pin description Publication Release Date: Aug. 28, 2009 - 5 - Revision A03 5. PIN DESCRIPTION PIN NUMBER PIN NAME FUNCTION DESCRIPTION 24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 A0A10 Address Multiplexed pins for row and column address. Row address: A0A10. Column address: A0A7. A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1. 22, 23 BS0, BS1 Bank Select Select bank to activate during row address latch time, or bank to read/write during address latch time. 2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76, 77, 79, 80, 82, 83, 85 DQ0DQ31 Data Input/ Output Multiplexed pins for data output and input. 20 CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. 19 RAS Row Address Strobe Command input. When sampled at the rising edge of the clock RAS , CAS and WE define the operation to be executed. 18 CAS Column Address Strobe Referred to RAS 17 WE Write Enable Referred to RAS 16, 28, 59, 71 DQM0DQM3 Input/Output Mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. 68 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock. 67 CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. 1, 15, 29, 43 VDD Power Power for input buffers and logic circuit inside DRAM. 44, 58, 72, 86 VSS Ground Ground for input buffers and logic circuit inside DRAM. 3, 9, 35, 41, 49, 55, 75, 81 VDDQ Power for I/O Buffer Separated power from VDD, to improve DQ noise immunity. 6, 12, 32, 38, 46, 52, 78, 84 VSSQ Ground for I/O Buffer Separated ground from VSS, to improve DQ noise immunity. 14, 21, 30, 57, 69, 70, 73 NC No Connection No connection. RadioFans.CN 196 MX29LV160DBTI-70G (HDMI : IC410) MX29LV160DBTI-70G Block Diagram RadioFans.CN 197 PCM5100 (HDMI:IC321) PCM5100 Block Diagram PCM510X (top view) Table 2. TERMINAL FUNCTIONS, PCM510 x TERMINAL I/ODESCRIPTION NAMENO. CPVDD1-Charge pump power supply, 3.3V CAPP2OCharge pump flying capacitor terminal for positive rail CPGND3-Charge pump ground CAPM4OCharge pump flying capacitor terminal for negative rail VNEG5ONegative charge pump rail terminal for decoupling, -3.3V OUTL6OAnalog output from DAC left channel OUTR7OAnalog output from DAC right channel AVDD8-Analog power supply, 3.3V AGND9-Analog ground DEMP10IDe-emphasis control for 44.1kHz sampling rate(1): Off (Low) / On (High) FLT11IFilter select : Normal latency (Low) / Low latency (High) SCK12ISystem clock input BCK13IAudio data bit clock input DIN14IAudio data input LRCK15IAudio data word clock input FMT16IAudio format selection : I2S (Low) / Left justified (High) XSMT17ISoft mute control : Soft mute (Low) / soft un-mute (High) LDOO18-Internal logic supply rail terminal for decoupling DGND19-Digital ground DVDD20-Digital power supply, 3.3V (1)Failsafe LVCMOS Schmitt trigger input Audio Interface 8x Interpolation Filter 32bit Modulator Current Segment DAC Current Segment DAC I/VI/V Analog Mute Analog Mute Zero Data Detector UVP/Reset PLL Clock Power Supply Ch. PumpPOR Clock Halt Detection Advanced Mute Control MCK BCK LRCK CAPP CAPM VNEG LINE OUT DIN (i2s) PCM510 x CPVDD (3.3V) AVDD (3.3V) DVDD (3.3V) GND Figure 1. PCM510 x Functional Block Diagram RadioFans.CN 198 AK5358BET (HDMI : IC451) AK5358BET Pin Function RadioFans.CN 199 AK4358VQ (HDMI : IC441) AK4358VQ Pin Function ASAHI KASEI AK4358 MS0203-J-01 2006/02 - 2 - ? AK4358VQ -40+85C 48pin LQFP AKD4358 評価 ? 配置 LOUT1- ROUT1+ 1 LOUT1+ 48 2 DZF33 DZF24 DZF15 CAD06 ACKSN7 PDN8 BICK9 MCLK10 DVDD ROUT1- 47 LOUT2+ 46 45 44 ROUT2-43 LOUT3+ 42 LOUT3- 41 ROUT3+ 40 ROUT3- 39 LOUT4+ 38 SDTI4 13 SDTI1 14 SDTI2 15 SDTI3 16 LRCK 17 18 CCLK/SCL 19 CDTI/SDA 20 CSN/CAD1 21 DCLK 22 DSDL4 23 36 35 34 33 32 31 30 29 28 27 26 AVSS AVDD VREFH ROUT4+ ROUT4- DIF0 DSDR3 DSDL3 DSDR2 DSDL2 DSDR1 AK4358VQ Top View I2C LOUT2- ROUT2+ LOUT4- 37DSDR4 24 11 DVSS12 25DSDL1 ASAHI KASEI AK4358 MS0203-J-01 2006/02 - 4 - PIN/FUNCTION No. Pin Name I/O Function 1 LOUT1- O DAC1 Lch Negative Analog Output Pin 2 LOUT1+ O DAC1 Lch Positive Analog Output Pin 3 DZF3 O Zero Input Detect 3 Pin 4 DZF2 O Zero Input Detect 2 Pin 5 DZF1 O Zero Input Detect 1 Pin 6 CAD0 I Chip Address 0 Pin 7 ACKSN I Auto Setting Mode Disable Pin (Pull-down Pin) “L”: Auto Setting Mode, “H”: Manual Setting Mode 8 PDN I Power-Down Mode Pin When at “L”, the AK4358 is in the power-down mode and is held in reset. The AK4358 should always be reset upon power-up. 9 BICK I Audio Serial Data Clock Pin 10 MCLK I Master Clock Input Pin An external TTL clock should be input on this pin. 11 DVDD - Digital Power Supply Pin, +4.75+5.25V 12 DVSS - Digital Ground Pin 13 SDTI4 I DAC4 Audio Serial Data Input Pin 14 SDTI1 I DAC1 Audio Serial Data Input Pin 15 SDTI2 I DAC2 Audio Serial Data Input Pin 16 SDTI3 I DAC3 Audio Serial Data Input Pin 17 LRCK I L/R Clock Pin 18 I2C I Control Mode Select Pin “L”: 3-wire Serial, “H”: I2C Bus 19 CCLK/SCL I Control Data Clock Pin I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I2C Bus) 20 CDTI/SDA I/O Control Data Input Pin I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I2C Bus) 21 CSN/CAD1 I Chip Select Pin I2C = “L”: CSN (3-wire Serial), I2C = “H”: CAD1 (I2C Bus) 22 DCLK I DSD Clock Pin 23 DSDL4 I DAC4 DSD Lch Data Input Pin 24 DSDR4 I DAC4 DSD Rch Data Input Pin 25 DSDL1 I DAC1 DSD Lch Data Input Pin 26 DSDR1 I DAC1 DSD Rch Data Input Pin 27 DSDL2 I DAC2DSD Lch Data Input Pin 28 DSDR2 I DAC2 DSD Rch Data Input Pin 29 DSDL3 I DAC3 DSD Lch Data Input Pin RadioFans.CN 200 ASAHI KASEI AK4358 MS0203-J-01 2006/02 - 4 - PIN/FUNCTION No. Pin Name I/O Function 1 LOUT1- O DAC1 Lch Negative Analog Output Pin 2 LOUT1+ O DAC1 Lch Positive Analog Output Pin 3 DZF3 O Zero Input Detect 3 Pin 4 DZF2 O Zero Input Detect 2 Pin 5 DZF1 O Zero Input Detect 1 Pin 6 CAD0 I Chip Address 0 Pin 7 ACKSN I Auto Setting Mode Disable Pin (Pull-down Pin) “L”: Auto Setting Mode, “H”: Manual Setting Mode 8 PDN I Power-Down Mode Pin When at “L”, the AK4358 is in the power-down mode and is held in reset. The AK4358 should always be reset upon power-up. 9 BICK I Audio Serial Data Clock Pin 10 MCLK I Master Clock Input Pin An external TTL clock should be input on this pin. 11 DVDD - Digital Power Supply Pin, +4.75+5.25V 12 DVSS - Digital Ground Pin 13 SDTI4 I DAC4 Audio Serial Data Input Pin 14 SDTI1 I DAC1 Audio Serial Data Input Pin 15 SDTI2 I DAC2 Audio Serial Data Input Pin 16 SDTI3 I DAC3 Audio Serial Data Input Pin 17 LRCK I L/R Clock Pin 18 I2C I Control Mode Select Pin “L”: 3-wire Serial, “H”: I2C Bus 19 CCLK/SCL I Control Data Clock Pin I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I2C Bus) 20 CDTI/SDA I/O Control Data Input Pin I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I2C Bus) 21 CSN/CAD1 I Chip Select Pin I2C = “L”: CSN (3-wire Serial), I2C = “H”: CAD1 (I2C Bus) 22 DCLK I DSD Clock Pin 23 DSDL4 I DAC4 DSD Lch Data Input Pin 24 DSDR4 I DAC4 DSD Rch Data Input Pin 25 DSDL1 I DAC1 DSD Lch Data Input Pin 26 DSDR1 I DAC1 DSD Rch Data Input Pin 27 DSDL2 I DAC2DSD Lch Data Input Pin 28 DSDR2 I DAC2 DSD Rch Data Input Pin 29 DSDL3 I DAC3 DSD Lch Data Input Pin 30 DSDR3 I DAC3 DSD Rch Data Input Pin 31 DIF0 I Audio Data Interface Format 0 Pin 32 ROUT4- O DAC4 Rch Negative Analog Output Pin 33 ROUT4+ O DAC4 Rch Positive Analog Output Pin 34 VREFH I Positive Voltage Reference Input Pin 35 AVDD - Analog Power Supply Pin, +4.75+5.25V 36 AVSS - Analog Ground Pin 37 LOUT4- O DAC4 Lch Negative Analog Output Pin 38 LOUT4+ O DAC4 Lch Positive Analog Output Pin 39 ROUT3- O DAC3 Rch Negative Analog Output Pin 40 ROUT3+ O DAC3 Rch Positive Analog Output Pin 41 LOUT3- O DAC3 Lch Negative Analog Output Pin 42 LOUT3+ O DAC3 Lch Positive Analog Output Pin 43 ROUT2- O DAC2 Rch Negative Analog Output Pin 44 ROUT2+ O DAC2 Rch Positive Analog Output Pin H27U1G8F2BTR-BC (HDMI : IC394) ASAHI KASEI AK4358 MS0203-J-01 2006/02 - 5 - 45 LOUT2- O DAC2 Lch Negative Analog Output Pin 46 LOUT2+ O DAC2 Lch Positive Analog Output Pin 47 ROUT1- O DAC1 Rch Negative Analog Output Pin 48 ROUT1+ O DAC1 Rch Positive Analog Output Pin Note: All input pins except pull-down pin should not be left floating. 絶対最大定格 (AVSS, DVSS=0V; Note 1) Parameter Symbol Min Max Units Power Supplies Analog Digital |AVSS-DVSS| (Note 2) AVDD DVDD GND -0.3 -0.3 - 6.0 6.0 0.3 V V V Input Current (any pins except for supplies) IIN - 10mA Digital Input Voltage VIND -0.3 DVDD+0.3 V Ambient Operating Temperature Ta -40 85 C Storage Temperature Tstg -65 150 C Note 1. 電圧対値。 Note 2. AVSSDVSS接続下。 注意: 値超条件使用場合、破壊。 通常動作保証。 推奨動作条件 (AVSS, DVSS=0V; Note 1) Parameter Symbol Min Typ Max Units Power Supplies (Note 3) Analog Digital AVDD DVDD 4.75 4.75 5.0 5.0 5.25 5.25 V V Voltage Reference VREF AVDD-0.5- AVDD V Note 3. AVDDDVDD立上考必要。 注意: 本記載条件以外使用関、当社責任負十分 注意下。 Rev 1.1 / Sep. 20095 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit) NAND Flash VCC VSS WP CLE ALE RE WE CEIO0IO7 R/B NC NC NC NCNC NCNC NC CLE ALEVss Vss Vss Vcc Vcc NC NC NC WP RE CE WERB NC NC NC NC NC NC NC NC NC NC NC NC NC I/O0 I/O1 I/O9 I/O2 I/O3 I/O10 I/O11I/O4 I/O15 I/O12I/O14 I/O13 I/O6 I/O7 I/O5 NC NCNCNC NC PRE I/O8 NC NCNC NCNC A B C D E F G H J K L M 1 2 3 4 5 6 7 8 9 10 ? ? ? Figure 2 : 48-TSOP1 / 63-FBGA Contact, x8 Device IO7 - IO0Data Input / Outputs CLECommand latch enable ALEAddress latch enable CEChip Enable RERead Enable WEWrite Enable WPWrite Protect R/BReady / Busy VccPower Supply VssGround NCNo Connection Figure 1 : Logic Diagram Table 1 : Signal Names ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? RadioFans.CN 201 H27U1G8F2BTR-BC Pin Function H27U1G8F2BTR-BC Block Diagram Rev 1.1 / Sep. 20096 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit) NAND Flash 1.2 PIN DESCRIPTION Table 2 : Pin Description NOTE : 1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. Pin NameDescription IO0 IO7 DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to High-Z when the device is deselected or the outputs are disabled. CLE COMMAND LATCH ENABLE This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write Enable (WE). ALE ADDRESS LATCH ENABLE This input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write Enable (WE). CE CHIP ENABLE This input controls the selection of the device. WE WRITE ENABLE This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge of WE. RE READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WP WRITE PROTECT The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase) operations. R/B READY BUSY The Ready/Busy output is an Open Drain pin that signals the state of the memory. Vcc SUPPLY VOLTAGE The Vcc supplies the power for all the operations (Read, Write, Erase). VssGROUND NCNO CONNECTION Rev 1.1 / Sep. 200915 1 H27U1G8F2B Series 1 Gbit (128 M x 8 bit) NAND Flash Figure 4 : Block Diagram ADDRESS REGISTER/ COUNTER PROGRAM ERASE CONTROLLER HV GENERATION COMMAND INTERFACE LOGIC COMMAND REGISTER DATA REGISTER IO RE BUFFERS Y DECODER PAGE BUFFER X D E C O D E R 1024 Mbit + 32 Mbit NAND Flash MEMORY ARRAY WP CE WE CLE ALE A27 A0 RadioFans.CN 202 A3V56S30FTP-G6 (HDMI:IC392,393) A3V56S30FTP A3V56S40FTP 256M Single Data Rate Synchronous DRAM Revision 1.1 Mar., 2010Page 2 / 39 CLK : Master Clock DQM : Output Disable / Write Mask (A3V56S30FTP) CKE : Clock Enable DQMU,L : Output Disable / Write Mask (A3V56S40FTP) /CS : Chip Select A0-12 : Address Input /RAS : Row Address Strobe BA0,1 : Bank Address /CAS : Column Address Strobe Vdd : Power Supply /WE : Write Enable VddQ : Power Supply for Output DQ0-7 : Data I/O (A3V56S30FTP) Vss : Ground DQ0-15 : Data I/O (A3V56S40FTP) VssQ : Ground for Output BA0 BA1 Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS A10(AP) A2 A3 Vdd A0 A1 Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0 BA1 A10(AP) A2 A3 Vdd A0 A1 DQM CKE Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE A12 A11 A8 A7 A6 A5 A4 Vss A9 Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC CLK A12 A11 A8 A7 A6 A5 A4 Vss A9 PIN CONFIGURATION (TOP VIEW) PIN CONFIGURATION (TOP VIEW) x8 x16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2332 2431 2530 2629 2728 RadioFans.CN 203 A3V56S30FTP-G6 Pin Function A3V56S30FTP A3V56S40FTP 256M Single Data Rate Synchronous DRAM Revision 1.1 Mar., 2010Page 4 / 39 Pin Descriptions SYMBOLTYPEDESCRIPTION CLKInput Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK