Denon-DVD2900-sacd-sm维修电路图 手册.pdf

SERVICE MANUAL MODELDVD-2900 DVD AUDIO-VIDEO / SUPER AUDIO CD PLAYER For U.S.A., Canada, Europe Cb Data (YCrCb output mode) 15, 21, 33, 61, 66, 72, 79, 85, 93, 114, 118, GNDIOPwrDigital Ground for I/O Power. 121, 126, 131, 144, 183, 190, 198 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 62 61 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 RSVD VDDCore GNDCore LCDPwrEn CBIank CSync VSync HSync Blue_Cb0 Blue_Cb1 Blue_Cb2 Blue_Cb3 Blue_Cb4 Blue_Cb5 GNDIO VDDIO Blue_Cb6 Blue_Cb7 Blue_Cb8 Blue_Cb9 GNDIO Green_Y0 Green_Y1 Green_Y2 Green_Y3 VDDIO Green_Y4 Green_Y5 Green_Y6 Green_Y7 Green_Y8 Green_Y9 GNDIO Red_Cr0 Red_Cr1 Red_Cr2 Red_Cr3 Red_Cr4 Red_Cr5 GNDCore VDDCore Red_Cr6 Red_Cr7 Red_Cr8 Red_Cr9 VidOutClk GNDCore BypPLLClk48M Clk48M GNDCore VDDCore ExtRefSel RSVD GNDCore VDDCore MemAddr3 MemAddr2 MemAddr1 MemAddr0 GNDIO MemAddr4 MemAddr5 MemAddr6 MemAddr7 GNDIO MemAddr8 MemAddr9 MemAddr10 MemAddr11 RSVD GNDIO VDDIO VDDIO RAS CAS WE DQM GNDIO MemData7 MemData6 MemData5 MemData4 MemData3 GNDIO MemData2 MemData1 MemData0 VDDIO PuPdDis MemData8 MemData9 GNDIO MemData10 MemData11 MemData12 MemData13 MemData14 GNDCore MemClk VDDCore GNDCore RSVD HostAddr5 HostAddr4 HostAddr3 HostAddr2 HostAddr1 HostAddr0 GNDCore HostCS HostRd_SDA HostWr_SCL VDDCore VidlnClk GNDIO VidlnData9 VidlnData8 VidlnData7 VidlnData6 VidlnData5 VidlnData4 VidlnData3 VidlnData2 VDDIO ExtRefXtalIOut ExtRefXtalIn VDDIO GNDIO MemData16 MemData17 MemData18 MemData19 GNDIO MemData20 MemData21 MemData22 MemData23 GNDIO MemData31 MemData30 GNDIO VDDIO MemData29 MemData28 GNDIO MemData27 MemData26 MemData25 MemData24 MemData15 BypPLLMemClk GNDCore VDDCore RSVD AVDD ARTN GNDCore VDDCore Clk54_72M BypPLLClk54_72M Test1 Test0 Reset VDDCore GNDIO SCKIn WSIn SDIn VDDIO SCKOut WSOut SDOut GNDIO VDDIO MemAddr12 DeintDone DetVideo Det22PD Det32PD GNDIO VDDIO HostData0 HostData1 HostData2 HostData3 HostData4 HostData5 HostData6HS HostData7VS RSVD HostData8VidlnData12 HostData9VidlnData13 HostData10VidlnData14 HostData11VidlnData15 VDDCore GNDCore HostData12VidlnData16 HostData13VidlnData17 HostData14VidlnData18 HostData15VidlnData19 GNDCore HostClk VDDCore HostMode HostAddr7 HostAddr6 TOP VIEW RSVD RSVD RadioFans.CN 43 43DVD-2900 16, 26, 73, 74, 89, 117, 132, VDDIOPwr3.3V I/O Power. 135, 182, 189, 194 2225, 2732Green_Y9:0OutGreen Data (RGB output mode);Y Data (YCrCb output mode) 3439, 4245Red_Cr9:0OutRed Data (RGB output mode); Cr Data (YCrCb output mode) 46VidOutClkOutVideo Output Clock, 36, 27 or 24 MHZ 48BypPLLClk48MInBypass PLL for Clk48M. 49Clk48MInOut 48 MHz Clock. 52ExtRefSelInExternal APLL Reference Select. 5760, 6265, 6770, 188 MemAddr12:0InOut SDRAM Address when an output. Configuration at reset when an input. 75RASOutSDRAM Row Address Strobe. 76CASOutSDRAM Column Address Strobe. 77WEOutSDRAM Write Enable. 78DQMOutSDRAM Data Mask. 8084, 8688, 91, 92, 9498, 109, 110113, MemData31:0InOut SDRAM Data. 115, 116, 119, 120, 122125, 127130 90PuPdDisInInternal pullup and pulldown disable test function. 101MemClkInOut SDRAM Clock. 108BypPLLMemClkInBypass PLL for MemClk. 133ExtRefXtalInInExternal APLL Reference Crystal/oscillator Input. 134ExtRefXtalOutOutExternal APLL Reference Crystal Output. 136143VidlnData9:2InMultiplexed Video Input Data;Y Video Input Data. 145VidlnClkInVideo Input Clock, 27.0 MHz 147HostWr_SCLIn186-Compatible Write when HostMode=0. Serial Clock when HostMode=1. 148HostRd_SDAInOut 186-Compatible Read when HostMode=0. Serial Data when HostMode=1. 149HostCSIn 186-Compatible Chip Select when HostMode=0. When HostMode=1, must be tied to VDD or pulled up to VDD. 151158HostAddr7:0In186-Compatible Address when HostMode=0. No connect when HostMode=1. 159HostModeInSerial Host Interface when HostMode=1. 186-compatible host interface when HostMode=0. 161HostClkInOut 186-Compatible Clock when HostMode=0. No connect when HostMode=1. 163166,HostData15:8 169172(VidInData19:2) InOut 186-Compatible Data when HostMode=0. Chroma video input data when HostMode=1. 174HostData7(VS)InOut 186-Compatible Data when HostMode=0.Vertical sync input when HostMode=1. 175HostData6(HS)InOut 186-Compatible Data when HostMode=0. Horizontal sync input when HostMode=1. 176181HostData5:0InOut 186-Compatible Data when HostMode=0. No connect when HostMode=1. 184Det32PDOut3:2 Pulldown Sequence Detected. 185Det22PDOut2:2 Pulldown Sequence Detected. 186DetVideoOutInterlaced Video Sequence Detected. 187DeintDoneOutDeinterlace processing complete for current field period. 191SDOutOutSerial Digital Audio Output Data. 192WSOutOutSerial Digital Audio Output Word Select. 193SCKOutOutSerial Digital Audio Output Clock. 195SDInInSerial Digital Audio Input Data. 196WSInInSerial Digital Audio Input Word Select. 197SCKInInSerial Digital Audio Input Clock. 200ResetInHardware Reset. 201, 202Test1:0InProduction hardware test support. 203BypPLLClk54_72MInBypass PLL for Clk54_72M. 204Clk54_72MInOut 54 or 72 MHz Clock. 207ARTNPwrAnalog Return for PLLs. 208AVDDPwr1.8V Analog Power for PLL. FunctionI/OPin No.Pin Name RadioFans.CN 44 44DVD-2900 CXD-2753R (MA: IC401) Pin Assignment Block Diagram RadioFans.CN 45 45DVD-2900 Terminal Functions Pin NameI/OFunctions 1VSC-It fixed to ground.( for Core) 2XMSLATILatch input for COM serial communication. 3MSCKIShift clock input for COM serial communication. 4MSDATIIData input for COM serial communication. 5VDC-+2.5V Power for Core. 6MSDATOOData output for COM serial communication. “Hi-Z” potential except the output mode. 7MSREADYOCompletion flag of output preparation for COM serial communication. “L” is outputted at the time of completion. 8XMSDOEOOutput enable pin for COM serial communication. “L” is outputted at the time of MSDATO mode. 9XRSTIReset pin. The whole IC is reset by at the time of “L” potential. 10SMUTEIpdSoft Mute. Soft mute of the audio output is carried out at the time of “H” potential. It releases at the time of “L” potential. 11MCKIIMaster Clock input. 12VSIO-It fixed to Ground. Ground for I/O. 13EXCKO1OExternal output Clock 1. 14EXCKO2OExternal output Clock 2. 15LRCKO44.1kHz, 1Fs Clock output. 16FRAMEOFrame signal output. 17VDIO-+3.3V Power for I/O. 18MNT0OMonitor output. 19MNT1OMonitor output. 20MNT2OMonitor output. 21MNT3OMonitor output. 22TESTOOOutput terminal for a Test. (open) 23TESTOOOutput terminal for a Test.(open) 24TESTOOOutput terminal for a Test.(open) 25TESTOOOutput terminal for a Test.(open) 26TCKIClock input for a Test. It fixed to “L” potential. 27TDIIpuInput pin(pull-up) for a Test.(open) 28VSC-It fixed to Ground. Ground for CORE. 29TDOOOutput for a Test.(open). 30TMSIpuInput pin(pull-up) for a Test.(open) 31TRSTIpuReset pin(pull-up) for a Test. Input the Power-on reset signal or fixed to “L” potential. 32TEST1ITest input pin. It fixed to “L” potential. 33TEST2ITest input pin. It fixed to “L” potential. 34TEST3ITest input pin. It fixed to “L” potential. 35VDC-+2.5V Power for CORE. 36TESTOOOut put for TEST. It fixed to open. 37XBITODST monitor. 38SUPDT0OSupplementary data output. (LSB) 39SUPDT1OSupplementary data output. 40SUPDT2OSupplementary data output. 41SUPDT3OSupplementary data output. 42VSIO-Ground for I/O. 43SUPDT4OSupplementary data output. 44SUPDT5OSupplementary data output. 45VDIO-+3.3V Power for I/O. 46SUPDT6OSupplementary data output. 47SUPDT7OSupplementary data output. (MSB) 48XSUPAKOSupplementary data Acknowledge output terminal. 49VSC-Ground for CORE. RadioFans.CN 46 46DVD-2900 50TESTOOOutput for TEST. (open) 51TESTIIInput for TEST. It fixed to “L” potential. 52TESTIIInput for TEST. It fixed to “L” potential. 53TESTOOOutput for TEST. (open) 54VDC-+2.5V Power for CORE. 55DSADMLODSD Data output terminal for Lch Down Mix. 56DSADMRODSD Data output terminal for Rch Down Mix. 57BCKASLII/O selection terminal of the Bit clock for DSD data output. L=input (Slave), H=output (Master) 58VSDSD-Ground terminal for DSD data output. 59BCKAIIBit clock input terminal for DSD data output. Input a Bit clock into this terminal at the time of BCKASL=”L” potential. 60BCKAOOBit clock output terminal for DSD data output. Bit clock output from this terminal at the time of BCKASL=”H” potential. 61PHREFIIReference phase signal input terminal for DSD output phase modulation. 62PHREFOOReference phase signal output terminal for DSD output phase modulation. 63ZDFLOLch zero-data detection flag (at the time of com setup). It will be set to “H” if non-sound data continues 300 msecs. 64DSALODSD data output terminal for Lch speaker. 65ZDFRORch zero-data detection flag (at the time of com setup). It will be set to “H” if non-sound data continues 300 msecs. 66DSARODSD data output terminal for Rch speaker. 67VDDSD-+3.3V Power for DSD data output. 68ZDFCOCch zero-data detection flag (at the time of com setup). It will be set to “H” if non-sound data continues 300 msecs. 69DSACODSD data output terminal for Cch speaker. 70ZDFLFEOLFEch zero-data detection flag (at the time of com setup). It will be set to “H” if non-sound data continues 300 msecs. 71DSASWODSD data output terminal for SWch speaker. 72VSDSD-Ground for DSD data output. 73ZDFLSOLSch zero-data detection flag (at the time of com setup). It will be set to “H” if non-sound data continues 300 msecs. 74DSALSODSD data output terminal for LSch speaker. 75ZDFRSORSch zero-data detection flag (at the time of com setup). It will be set to “H” if non-sound data continues 300 msecs. 76DSARSODSD data output terminal for RSch speaker. 77VDDSDO+3.3V Power for DSD data output. 78IOUT0OData output terminal 0 for IEEE1394 link chip I/F. 79IOUT1OData output terminal 1 for IEEE1394 link chip I/F. 80VSC-Ground for CORE. 81IOUT2OData output terminal 2 for IEEE1394 link chip I/F. 82IOUT3OData output terminal 3 for IEEE1394 link chip I/F. 83VDC-+2.5V Power for CORE. 84IOUT4OData output terminal 4 for IEEE1394 link chip I/F. 85IOUT5OData output terminal 5 for IEEE1394 link chip I/F. 86VSIO-Ground for I/O. 87IANCOOTransmission information data output terminal for IEEE1394 link chip I/F. 88IFULLIData transmission hold request signal input terminal for IEEE1394 link chip I/F. 89IEMPTYIHigh speed transmission request signal input terminal for IEEE1394 link chip I/F. 90VDIO-+3.3V Power for I/O. 91IFRMOFrame reference signal output terminal for IEEE1394 link chip I/F. 92IOUTEOEnable signal output terminal for IEEE1394 link chip I/F. 93IBCKOData transmission clock output terminal for IEEE1394 link chip I/F. 94VSC-Ground for CORE. 95TESTIITEST input terminal. It fixed to “H” potential. Pin NameI/OFunctions RadioFans.CN 47 47DVD-2900 96TESTIITEST input terminal. It fixed to “L” potential. 97TESTIIpuTEST input terminal. It fixed to “H” potential. 98TESTOOTEST output terminal. (open) 99VDC-+2.5V Power for CORE. 100TESTIITEST input terminal. It fixed to “L” potential. 101TESTIITEST input terminal. It fixed to “L” potential. 102TESTIITEST input terminal. It fixed to “L” potential. 103TESTIITEST input terminal. It fixed to “L” potential. 104TESTIITEST input terminal. It fixed to “L” potential. 105TESTIITEST input terminal. It fixed to “L” potential. 106VSIO-Ground for I/O. 107TESTIITEST input terminal. It fixed to “L” potential. 108TESTIITEST input terminal. It fixed to “L” potential. 109TESTIITEST input terminal. It fixed to “L” potential. 110VDIO-+3.3V Power for I/O. 111WAD0IExternal A/D data input terminal(LSB) for PSP physical disc mark detection. 112WAD1IExternal A/D data input terminal for PSP physical disc mark detection. 113WAD2IExternal A/D data input terminal for PSP physical disc mark detection. 114WAD3IExternal A/D data input terminal for PSP physical disc mark detection. 115VSIO-Ground for I/O. 116VSC-Ground for CORE. 117WAD4IExternal A/D data input terminal for PSP physical disc mark detection. 118WAD5IExternal A/D data input terminal for PSP physical disc mark detection. 119WAD6IExternal A/D data input terminal for PSP physical disc mark detection. 120WAD7IExternal A/D data input terminal(MSB) for PSP physical disc mark detection. 121VDC-+2.5V Powe for CORE. 122TESTIITEST input terminal. It fixed to “L” potential. 123WCKIOperation clock for PSP physical disc mark detection. 124WAVDD-+2.5V Power. A/D Power supply for PSP physical disc mark detection. 125WAVDD-+2.5V Power. A/D Power supply for PSP physical disc mark detection. 126WARFIAiAnalog RF signal input terminal for PSP physical disc mark detection. 127WAVRBAiA/D bottom reference terminal for PSP physical disc mark detection. 128WAVSS-A/D Ground terminal for PSP physical disc mark detection. 129WAVSS-A/D Ground terminal for PSP physical disc mark detection. 130VSIO-Ground for I/O. 131DQ7I/OSDRAM data input/output terminal. (MSB) 132DQ6I/OSDRAM data input/output terminal. 133DQ5I/OSDRAM data input/output terminal. 134DQ4I/OSDRAM data input/output terminal. 135VDIO-+3.3V Power for I/O. 136DQ3I/OSDRAM data input/output terminal. 137DQ2I/OSDRAM data input/output terminal. 138DQ1I/OSDRAM data input/output terminal. 139DQ0I/OSDRAM data input/output terminal. (LSB) 140VSIO-Ground for I/O. 141DCLKOClock output terminal for SDRAM. 142DCKEOClock enable output terminal for SDRAM. 143XWEOWrite enable output terminal for SDRAM. 144XCASOColomn address strobe output terminal for SDRAM. 145XRASORow address strobe output terminal for SDRAM. 146VDIO-+3.3V Power for I/O. 147TESTOOOutput terminal for TEST. (open) Pin NameI/OFunctions RadioFans.CN 48 48DVD-2900 Ipu: Pull-up input Ipd: Pull-down input Ai: Analog input 148A11OAddress output terminal for SDRAM. (MSB) 149A10OAddress output terminal for SDRAM. 150VSC-Ground for CORE. 151A9OAddress output terminal for SDRAM. 152A8OAddress output terminal for SDRAM. 153VDC-+2.5V Power for CORE. 154A7OAddress output terminal for SDRAM. 155A6OAddress output terminal for SDRAM. 156A5OAddress output terminal for SDRAM. 157A4OAddress output terminal for SDRAM. 158VSIO-Ground for I/O. 159A3OAddress output terminal for SDRAM. 160A2OAddress output terminal for SDRAM. 161A1OAddress output terminal for SDRAM. 162A0OAddress output terminal for SDRAM. (LSB) 163VDIO-+3.3V Power for I/O. 164XSRQOOutput terminal of the Data Request signal inputted a front-end processor. 165XSHDIInput terminal of the header Flag outputted from a front-end processor. 166SDCKIInput terminal of the data conveyance Clock outputted from a front-end processor. 167XASKIInput terminal of the data valid Flag outputted from a front-end processor. 168SDEFIInpu