HarmanKardon-AVR3550HD-avr-sm2维修电路原理图.pdf

1.1 Features TMP86F409NG 9. 8bit Serial Expansion Interface (SEI): 1 channel (MSB/LSB selectable and max. 4Mbps at 16MHz) 10.10-bit successive approximation type AD converter - Analog input: 6 ch 11. Key-on wakeup : 4 channels 12. Clock operation Single clock mode Dual clock mode 13. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high fre- quency clock. Release by falling edge of the source clock which is set by TBTCR. IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interru- puts(CPU restarts). IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by inter- ruputs. (CPU restarts). SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low fre- quency clock.Release by falling edge of the source clock which is set by TBTCR. SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interru- put.(CPU restarts). SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by interruput. 14.Wide operation voltage: 4.5 V to 5.5 V at 16MHz /32.768 kHz 2.7 V to 5.5 V at 8 MHz /32.768 kHz AVR3550HD harman/kardonharman/kardon RadioFans.CN TMP86F409NG 1.2Pin Assignment Figure 1-1 Pin Assignment 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSS XOUT TEST VDD (XTIN) P21 (XTOUT) P22 RESET (STOP/INT5) P20 (TXD) P00 (SCLK) P02 (MISO) P04 (MOSI) P03 P14 P16 P30 (TC3/PDO3/PWM3) P32 (AIN0) P33 (AIN1) P35 (AIN3/STOP3) P34 (AIN2/STOP2) P37 (AIN5/STOP5) P36 (AIN4/STOP4) P31 (TC4/PDO4/PWM4/PPG4) (RXD) P01 XIN P15 P05 (SS) P06 (INT3/PPG) P07 (TC1/INT4) P12 (DVO) P10 (INT0) P13 P11 (INT1) AVR3550HD harman/kardonharman/kardon RadioFans.CN 1.3 Block Diagram TMP86F409NG 1.3Block Diagram Figure 1-2 Block Diagram AVR3550HD harman/kardonharman/kardon RadioFans.CN TMP86F409NG 1.4Pin Names and Functions The TMP86F409NG has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pin functions in MCU mode. The serial PROM mode is explained later in a separate chapter. Table 1-1 Pin Names and Functions(1/2) Pin NamePin NumberInput/OutputFunctions P07 TC1 INT4 21 IO I I PORT07 TC1 input External interrupt 4 input P06 INT3 PPG 20 IO I O PORT06 External interrupt 3 input PPG output P05 SS 19 IO I PORT05 SEI master/slave select input P04 MISO 14 IO IO PORT04 SEI master input, slave output P03 MOSI 13 IO IO PORT03 SEI master input, slave output P02 SCLK 12 IO IO PORT02 SEI serial clock input/output pin P01 RXD 11 IO I PORT01 UART data input P00 TXD 10 IO O PORT00 UART data output P1616IOPORT16 P1517IOPORT15 P1415IOPORT14 P1318IOPORT13 P12 DVO 24 IO O PORT12 Divider Output P11 INT1 23 IO I PORT11 External interrupt 1 input P10 INT0 22 IO I PORT10 External interrupt 0 input P22 XTOUT 7 IO O PORT22 Resonator connecting pins(32.768kHz) for inputting external clock P21 XTIN 6 IO I PORT21 Resonator connecting pins(32.768kHz) for inputting external clock P20 INT5 STOP 9 IO I I PORT20 External interrupt 5 input STOP mode release signal input P37 AIN5 STOP5 32 IO I I PORT37 Analog Input5 STOP5 P36 AIN4 STOP4 31 IO I I PORT36 Analog Input4 STOP4 84 AVR3550HD harmanharman/kardon/kardon TMP86F409NG P35 AIN3 STOP3 30 IO I I PORT35 Analog Input3 STOP3 P34 AIN2 STOP2 29 IO I I PORT34 Analog Input2 STOP2 P33 AIN1 28 IO I PORT33 Analog Input1 P32 AIN0 27 IO I PORT32 Analog Input0 P31 TC4 PDO4/PWM4/PPG4 26 IO I O PORT31 TC4 input PDO4/PWM4/PPG4 output P30 TC3 PDO3/PWM3 25 IO I O PORT30 TC3 input PDO3/PWM3 output XIN2IResonator connecting pins for high-frequency clock XOUT3OResonator connecting pins for high-frequency clock RESET8IReset signal TEST4ITest pin for out-going test. Normally, be fixed to low. VDD5I+5V VSS1I0(GND) Table 1-1 Pin Names and Functions(2/2) Pin NamePin NumberInput/OutputFunctions 85 AVR3550HD harmanharman/kardon/kardon 3 Revision 1.9 256M Double Data Rate Synchronous DRAM A3S56D30ETP A3S56D40ETP Pin Assignment (Top View) 66-pin TSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS 66pin TSOP(II) 400mil width x 875mil length 0.65mm Lead Pitch Row A0-12 Column A0-9 (x8) A0-8 (x16) VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS x8 x16 CLK, /CLK CKE /CS /RAS /CAS /WE DQ0-15 UDM, LDM DM DQ0-7 UDQS, LDQS DQS : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O (x16) : Write Mask (x16) : Write Mask (x8) : Data I/O (x8) : Data Strobe (x16) : Data Strobe (x8) A0-12 BA0,1 Vdd VddQ Vss VssQ : Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output 86 AVR3550HD harman/kardonharman/kardon 4 Revision 1.9 256M Double Data Rate Synchronous DRAM A3S56D30ETP A3S56D40ETP PIN FUNCTION CLK, /CLKInput Clock: CLK and /CLK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of /CLK. Output (read) data is referenced to the crossings of CLK and /CLK (both directions of crossing). CKEInput Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. /CSInputChip Select: When /CS is high, any command means No Operation. /RAS, /CAS, /WEInputCombination of /RAS, /CAS, /WE defines basic commands. A0-12Input A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. BA0,1Input DQ0-7 (x8), DQ0-15 (x16), Input / Output DQS (x8) Vdd, VssPower SupplyPower Supply for the memory array and peripheral circuitry. VddQ, VssQPower SupplyVddQ and VssQ are supplied to the Output Buffers only. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data Input/Output: Data bus Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15 SYMBOLTYPEDESCRIPTION DM (x8) Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7; UDM corresponds to the data on DQ8-DQ15. Input / Output VrefInputSSTL_2 reference voltage. UDQS, LDQS (x16) UDM, LDM (x16) 87 AVR3550HD harman/kardonharman/kardon 5 Revision 1.9 256M Double Data Rate Synchronous DRAM A3S56D30ETP A3S56D40ETP BLOCK DIAGRAM /CS/RAS /CAS/WEDM Memory Array Bank #0 DQ0 - 7 I/O Buffer Memory Array Bank #1 Memory Array Bank #2 Memory Array Bank #3 Mode Register Control Circuitry Address Buffer A0-12 BA0,1 Clock Buffer CLKCKE Control Signal Buffer DQS Buffer DQS DLL /CLK A3S56D30ETP Type Designation Code This rule is applied to only Synchronous DRAM family. Zentel DRAM Speed Grade Package Type TP: TSOP(II) Process Generation Function Reserved for Future Use Organization 2n3: x8 DDR Synchronous DRAM Density 56: 256M bits Interface S:SSTL_3, _2 Memory Style (DRAM) A 3 S 56 D 3 0 E TP G5 6: 166MHz CL=3.0/2.5, and 133MHz CL=2.0 5: 200MHz CL=3.0, 166MHz CL=2.5, and 133MHz CL=2.0 5E: 200MHz CL=3.0/2.5, and 133MHz CL=2.0 88 AVR3550HD harman/kardonharman/kardon 6 Revision 1.9 256M Double Data Rate Synchronous DRAM A3S56D30ETP A3S56D40ETP BLOCK DIAGRAM /CS/RAS /CAS/WEUDM, LDM Memory Array Bank #0 DQ0 - 15 I/O Buffer Memory Array Bank #1 Memory Array Bank #2 Memory Array Bank #3 Mode Register Control Circuitry Address Buffer A0-12 BA0,1 Clock Buffer CLKCKE Control Signal Buffer DQS Buffer UDQS, LDQS DLL /CLK A3S56D40ETP Type Designation Code This rule is applied to only Synchronous DRAM family. Zentel DRAM Speed Grade Package Type TP: TSOP(II) Process Generation Function Reserved for Future Use Organization 2n4: x16 DDR Synchronous DRAM Density 56: 256M bits Interface S:SSTL_3, _2 Memory Style (DRAM) A 3 S 56 D 4 0 E TP G5 6: 166MHz CL=3.0/2.5, and 133MHz CL=2.0 5: 200MHz CL=3.0, 166MHz CL=2.5, and 133MHz CL=2.0 5E: 200MHz CL=3.0/2.5, and 133MHz CL=2.0 89 AVR3550HD harman/kardonharman/kardon Excel Semiconductor inc. ES29LV320E 32Mbit(4M x 8/2M x 16) CMOS 3.0 Volt-only, Boot Sector Flash Memory GENERAL FEATURES Single power supply operation - 2.7V 3.6V for read, program and erase operations Sector Structure - 8Kbyte x 8 boot sectors - 64Kbyte x 63 sectors - 256byte security sector Top or Bottom boot block - ES29LV320ET for Top boot block device - ES29LV320EB for Bottom boot block device A 256 bytes of extra sector for security code - Factory locked - Customer lockable Package Options - 48-pin TSOP - 48-ball FBGA - Pb-free packages - All Pb-free products are RoHS-Compliant Low Vcc write inhibit Manufactured on 0.18um process technology Compatible with JEDEC standards - Pinout and software compatible with single-power supply flash standard DEVICE PERFORMANCE Read access time - 70ns/90ns for normal Vcc range ( 2.7V 3.6V ) Program and erase time - Program time : 6us/byte, 8us/word ( typical ) - Accelerated program time : 4us/word ( typical ) - Sector erase time : 0.7sec/sector ( typical ) Power consumption (typical values) - 15uA in standby or automatic sleep mode - 10mA active read current at 5MHz - 15mA active write current during program or erase Minimum 100,000 program/erase cycles per sector 20 Year data retention at 125oC SOFTWARE FEATURES Erase Suspend / Erase Resume Data# poll and toggle for Program/erase status CFI ( Common Flash Interface) supported Unlock Bypass Program Autoselect mode Auto-sleep mode after tACC + 30ns HARDWARE FEATURES Hardware reset input pin (RESET#) - Provides a hardware reset to device - Any internal device operation is terminated and the device returns to read mode by the reset Ready/Busy# output pin (RY/BY#) - Provides a program or erase operational status about whether it is finished for read or still being progressed WP#/ACC input pin - Two outermost boot sectors are protected when WP# is set to low, regardless of sector protection - Program speed is accelerated by raising WP#/ACC to a high voltage (11.5V12.5V) Sector protection / unprotection (RESET# , A9 ) - Hardware method of locking a sector to prevent any program or erase operation within that sector - Two methods are provided : - In-system method by RESET# pin - A9 high-voltage method for PROM programmers Temporary Sector Unprotection (RESET# ) - Allows temporary unprotection of previously protected sectors to change data in-system 90 AVR3550HD harman/kardonharman/kardon Excel Semiconductor inc. The ES29LV320 is a 32 megabit, 3.0 volt-only flash memory device, organized as 4M x 8 bits (Byte mode) or 2M x 16 bits (Word mode) which is config- urable by BYTE#. Eight boot sectors and sixty three main sectors with uniform size are provided : 8Kbytes x 8 and 64Kbytes x 63. The device is man- ufactured with ESIs proprietary, high performance and highly reliable 0.18um CMOS flash technology. The device can be programmed or erased in-sys- tem with standard 3.0 Volt Vcc supply ( 2.7V3.6V) and can also be programmed in standard EPROM programmers. The device offers minimum endur- ance of 100,000 program/erase cycles and more than 10 years of data retention. The ES29LV320 offers access time as fast as 70ns or 90ns, allowing operation of high-speed micropro- cessors without wait states. Three separate control pins are provided to eliminate bus contention : chip enable (CE#), write enable (WE#) and output enable (OE#). All program and erase operation are automatically and internally performed and controlled by embed- ded program/erase algorithms built in the device. The device automatically generates and times the necessary high-voltage pulses to be applied to the cells, performs the verification, and counts the num- ber of sequences. Some status bits (DQ7, DQ6 and DQ5) read by data# polling or toggling between consecutive read cycles provide to the users the internal status of program/erase operation: whether it is successfully done or still being progressed. Extra Security Sector of 256 bytes In the device, an extra security sector of 256 bytes is provided to customers. This extra sector can be used for various purposes such as storing ESN (Electronic Serial Number) or customers security codes. Once after the extra sector is written, it can be permanently locked by the device manufacturer (factory-locked) or a customer(customer-lockble). At the same time, a lock indicator bit (DQ7) is per- manently set to a 1 if the part is factory- locked, or set to 0 if it is customer-lockable. Therefore, this lock indicator bit (DQ7) can be properly used to avoid that any customer-lockable part is used to replace a factory-locked part. The extra security sector is an extra memory space for customers when it is used as a customer-lockable version. So, it can be read and written like any other sectors. But it should be noted that the number of E/W(Erase and Write) cycles is limited to 300 times (maximum) only in the Security Sector. Special services such as ESN and factory-lock are available to customers (ESIs Special-Code service ) The ES29LV320 is completely compatible with the JEDEC standard command set of single power sup- ply Flash. Commands are written to the internal command register using standard write