AudioAccess-MA361CP-pwr-sm维修电路原理图.pdf

AUDIOACCESS MA-361/MA-361CP TWELVE CHANNEL DIGITAL AMPLIFIER PRELIMINARY SERVICE MANUAL Harman Consumer Group 250 Crossways Park Dr. Woodbury, New York 11797 RadioFans.CN 收音机爱 好者资料库 FEATURES The Audioaccess MA-361 Twelve Channel Digital Amplifier designed, engineered and manufactured by Madrigal in Middletown, CT represents the product of over two years of research and development. As the inventor of the 12 channel amplifier category, Audioaccess has reinvented this category with the introduction of the MA-361. The goals for the MA-361 were clear: high power, low distortion, quiet, cool operation, outstanding sonics and ease of installation, when used not only in Audioaccess systems, but also with other home and commercial audio distribution systems. The trend towards higher quality and larger speakers for custom installed applications has created a need for this amp. We believe you will agree that the MA-361 is the first in an entirely new class of twelve channel amplifiers. Unique features The main features of the MA-361 include a conservative power rating of 100 Watts per channel into 8 Ohms from 20Hz- 20kHz with all channels driven at 93% efficiency. This amazing efficiency not only minimizes power consumption, it also runs surprisingly cool. Other unique features include programmable 7-band graphic EQ (set by the installer via PC) for each zone and optional plug-in stereo Volume/Tone Control Modules, which pro-vide volume control in Expansion rooms/sub zones within an Audioaccess system or another RS-232 based control system. The modular layout permits the dealer to easily replace individual amplifier modules should service ever be required. An external speaker termination board can be ordered in advance to allow termination of loudspeakers before the amplifier is delivered for final installation. At final, simply plug the speaker termination board onto the rear panel of the amplifier. Other features To make the amplifier specifically attractive for use in whole-house audio distribution, we have included specific features to ensure reliable and easy installation. Signal sensing and voltage triggers activate the main power in each stereo zone of amplification. Dip switches on the rear-panel configure the MA-361 for use in either mono or stereo operation. A simple bussing scheme allows audio signals to be routed into a single zone, selected zones, or all areas. 7-Band Graphic Equalization The MA-361s 7-band graphic equalization capabilities allows the installing dealer to custom tailor the sound in each zone to compensate for the different room acoustics throughout a residence, maximizing the performance of each pair of speakers. This is accomplished by using the Audioaccess Installation Manager Software application (or stand-alone application) running on the dealers PC or laptop. Signal Sensing and Voltage Triggers The signal sensing capabilities of the MA-361 ensure that the amplifiers for a given zone are only powered on when a particular area is active, saving on energy consumption. Voltage triggers allow the MA-361 to automatically turn on accessory items such as a fan, or a separate device when either the amplifier or a designated zone is activated. Volume/Tone Control Modules Optional Volume/Tone Control Modules, which plug into available slots inside the amplifier, provide the ability to supply high power at very low distortion levels to expansion rooms within the multi-room system. The user may control the volume in rooms with Audioaccess keypads and touchscreens, or by using ANY other touch screen/control systems. A total of 6 Volume/Tone Control Modules may be installed in the MA-361. Flexible Installation Capabilities The MA-361 is designed for use with Audioaccess systems, as well as other Multi-room or RS-232 based systems. The unit is programmed with the proprietary Installation Manager application when it is used with other Audioaccess Multi- Room components. Configuration settings are downloaded from a Windows PC or laptop via the RS-485 communication port on the MA-361. When used with other RS-232 based systems, a separate application is available, which downloads amplifier configuration settings via the RS-232 port on the MA-361CP version. Summary The MA-361s combination of power capabilities, sonic quality, features, programming ease, installation flexibility and serviceability clearly sets the new standard for amplifiers within the multi-room category. RadioFans.CN 收音机爱 好者资料库 Specifications: Number of Channels: 12, configured as 6 left/right mono or stereo pairs (zones) Power Output: 100 Watts 8 ohms, from 20Hz 20kHz, all channels driven 130 Watts 4 ohms, from 20Hz 20kHz, all channels driven 200 Watts 4 ohms, from 20Hz 20kHz, two channels driven Efficiency: 93% 100 Watts/8 ohms THD the byte-wide (x8) data appears on DQ7-DQ0. This device is designed to be programmed in-system using only a single 3.0 volt VCC supply. No VPP is required for write or erase operations. The device can also be programmed in standard EPROM programmers. This device is manufactured using AMDs 0.32 m process technology, and offers all the features and ben- efits of the Am29LV200, which was manufactured using 0.5 m process technology. In addition, the Am29LV200B features unlock bypass programming and in-system sector protection/unprotection. The standard device offers access times of 55, 70, 90 and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Com- mands are written to the command register using standard microprocessor write timings. Register con- tents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithman internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithman internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via pro- gramming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMDs Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. 4Am29LV200B PRODUCT SELECTOR GUIDE Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM Family Part NumberAm29LV200B Speed Options Regulated Voltage Range: VCC = 3.03.6 V55R Full Voltage Range: VCC = 2.73.6 V7090120 Max access time, ns (tACC)557090120 Max CE# access time, ns (tCE)557090120 Max OE# access time, ns (tOE)30303550 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator Timer VCC Detector State Control Command Register VCC VSS WE# BYTE# CE# OE# STB STB DQ0DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address Latch A0A16 Am29LV200B5 CONNECTION DIAGRAMS A1 A15 NC A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A7 A6 A5 A4 A3 A2 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 A16 DQ2 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 A1 A15 NC A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A7 A6 A5 A4 A3 A2 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 A16 DQ2 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 Reverse TSOP Standard TSOP 6Am29LV200B CONNECTION DIAGRAMS PIN CONFIGURATION A0A16=17 addresses DQ0DQ14 =15 data inputs/outputs DQ15/A-1=DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE#=Selects 8-bit or 16-bit mode CE#=Chip enable OE#= Output enable WE#=Write enable RESET#=Hardware reset pin, active low RY/BY#= Ready/Busy# output VCC =3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VSS=Device ground NC=Pin not connected internally LOGIC SYMBOL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC RY/BY# NC A7 A6 A5 A4 A3 A2 A1 A0 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC SO 17 16 or 8 DQ0DQ15 (A-1) A0A16 CE# OE# WE# RESET# BYTE#RY/BY# 1/33March 2000 M29W800AT M29W800AB 8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Low Voltage Single Supply Flash Memory I2.7V to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS IACCESS TIME: 80ns IPROGRAMMING TIME: 10s typical IPROGRAM/ERASE CONTROLLER (P/E.C.) Program Byte-by-Byte or Word-by-Word Status Register bits and Ready/Busy Output ISECURITY PROTECTION MEMORY AREA IINSTRUCTION ADDRESS CODING: 3 digits IMEMORY BLOCKS Boot Block (Top or Bottom location) Parameter and Main blocks IBLOCK, MULTI-BLOCK and CHIP ERASE IMULTI BLOCK PROTECTION/TEMPORARY UNPROTECTION MODES IERASE SUSPEND and RESUME MODES Read and Program another Block during Erase Suspend ILOW POWER CONSUMPTION Stand-by and Automatic Stand-by I100,000 PROGRAM/ERASE CYCLES per BLOCK I20 YEARS DATA RETENTION Defectivity below 1ppm/year IELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M29W800AT: D7h Bottom Device Code, M29W800AB: 5Bh Figure 1. Logic Diagram AI02599 19 A0-A18 W DQ0-DQ14 VCC M29W800AT M29W800AB E VSS 15 G RP DQ15A1 BYTE RB 44 1 FBGA TSOP48 (N) 12 x 20mm SO44 (M) LFBGA48 (ZA) 8 x 6 solder balls M29W800AT, M29W800AB 2/33 Figure 2. TSOP Connections DQ3 DQ9 DQ2 A6 DQ0 W A3 RB DQ6 A8 A9 DQ13 A17 A10DQ14 A2 DQ12 DQ10 DQ15A1 VCC DQ4 DQ5 A7 DQ7 NC NC AI02179 M29W800T M29W800B 12 1 13 2425 36 37 48 DQ8 NC NC A1 A18 A4 A5 DQ1 DQ11 G A12 A13 A16 A11 BYTE A15 A14 VSS E A0 RP VSS Figure 3. SO Connections G DQ0 DQ8 A3 A0 E VSS A2 A1 A13 VSS A14 A15 DQ7 A12 A16 BYTE DQ15A1 DQ5DQ2 DQ3 VCCDQ11 DQ4 DQ14 A9 W RB A4 RP A7 AI02181 M29W800T M29W800B 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 2322 20 19 18 17DQ1 DQ9 A6 A5 DQ6 DQ13 44 39 38 37 36 35 34 33 A11 A10 DQ10 21 DQ12 40 43 1 42 41 A17A8 A18 Table 1. Signal Names A0-A18Address Inputs DQ0-DQ7Data Input/Outputs, Command Inputs DQ8-DQ14Data Input/Outputs DQ15A1Data Input/Output or Address Input EChip Enable GOutput Enable WWrite Enable RPReset/Block Temporary Unprotect RBReady/Busy Output BYTEByte/Word Organization VCCSupply Voltage VSSGround NCNot Connected Internally DUDont Use as Internally Connected DESCRIPTION TheM29W800A isa non-volatilememory that may be erasedelectrically at the block or chip level and programmed in-system on a Byte-by-Byte or Word-by-Word basis using only a single 2.7V to 3.6V VCCsupply. For Program and Erase opera- tions the necessary high voltages are generated internally. The device can also be programmed in standard programmers. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Blocks canbe protected against pro- graming and erase on programming equipment, and temporarily unprotected to make changes in the application. Each block can be programmed and erased over 100,000 cycles. Instructions for Read/Reset, Auto Select for read- ing the Electronic Signature or Block Protection status, Programming, Block and Chip Erase, Erase Suspend and Resume are written to the de- vice in cycles of commands to a Command Inter- face using standard microprocessor write timings. The device is offered in TSOP48 (12 x 20mm), SO44 and LFBGA48 0.8 mm ball pitch packages. 1999 Microchip Technology Inc.DS40139E-page 1 Devices included in this Data Sheet: PIC12C508 PIC12C508A PIC12CE518 PIC12C509 PIC12C509A PIC12CE519 PIC12CR509A Note:Throughout this data sheet PIC12C5XX refers to the PIC12C508, PIC12C509, PIC12C508A, PIC12C509A, PIC12CR509A, PIC12CE518 and PIC12CE519. PIC12CE5XX refers to PIC12CE518 and PIC12CE519. High-Performance RISC CPU: Only 33 single word instructions to learn All instructions are single cycle (1 s) except for program branches which are two-cycle Operating speed: DC - 4 MHz clock input DC - 1 s instruction cycle 12-bit wide instructions 8-bit wide data path Seve