Arcam-Alpha8-cd-sm维修电路原理图.pdf
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1、ALPHA 7/8/9 CD SERVICE MANUALALPHA 7/8/9 CD SERVICE MANUALArcam Alpha 7/8/9 CD Service ManualIssue 1 Serial No. 0001 - (Paul Newton July 96)Circuit DescriptionThe following notes describe the operation of theAlpha 7/8/9 CD players. They include the circuitry onthe main, DAC and display PCBs but not
2、that on theservo PCB attached to the mechanism.Power SuppliesThe mains input is fitted with inductors L2,3,6,7 tofilter electromagnetic interference coming out of theplayer.Mains transformer T201 has three secondarywindings supplying two separate power supplies andan AC supply for the display filame
3、nt:Analogue SupplyBridge rectifier D4,5,6,7 and reservoir capacitorsC209-C212 produce unregulated split rails of about+/-22V.Z204 and Z205 provide regulated outputs of +18Vand -18V respectively that power the opamps in theaudio output stage. Since there is no power switch on this secondary, theanalo
4、gue supplies are always connected.Digital SupplySwitch SW201-A disconnects the digital secondarywinding when the Power switch is out.An unregulated supply of about 11V is produced bythe bridge rectifier D8,9,10,11 and reservoircapacitor C36.This is then regulated to provide three +5 voltsupplies (Z2
5、08 general logic supply, Z207 DACsupply, Z203 system clock generator supply) and a+7.3v supply for themechanism and motor drivecircuits(Z206).A -30v supply is formed by Z209 and associatedcomponents to power the display grid.MutingWhen the unit is turned off SW201-A dischargescapacitor C29 quickly.
6、This along with the AMUTEsignal from the microprocessor, controls the outputmute transistors Q1,101 via level shifter Q3.Clock GeneratorThe system clock is generated by a discrete oscillatorbased around Q2 and 16.9344MHz oscillator X1. Theoutput of Q2 is amplified and buffered by invertersZ202-E & D
7、 and sent to the clock input of the DACZ201. DAC & Audio Outputs (Alpha 7 only)The DAC is a Delta-Sigma design from Burr Brown,the PCM1710U.The serial digital data from the decoder Z206 is inputto pins 1 to 3. The system clock is input to pin 5. The DAC is powered entirely from one 5V supply,althoug
8、h it is split and decoupled between theanalogue and digital sections of the device.The analogue outputs from each channel areprocessed identically.Three poles of filtering areprovided by the active filter based around Z1-A. Z1-Bbuffers the audio output and sets the output level.Muting is provided by
9、 turning on Q1 and Q101.DAC & Audio Outputs (Alpha 8 only)This is a similar circuit as the one used on the ArcamAlpha 6 DAC PCB but designed for Sony formatinput data and a better digital filter, the SM5843AP1,Z14.The digital filter is used with a SM5864AP 20-bitDAC chip, Z12, (described here as a P
10、WM noiseshaper to avoid confusion with the 1-bit DAC Latchwhich follows it). The output from this is re-latched byZ7, Z8.Digital FilterA PIC micro on the mother boardcontrols the filter with the signals RB0 to RB7. TheSM5843 filter has internal pull-up resistors on itsinputs resulting in RB4 & RB5 b
11、eing logic 1.The SM5843APT requires several control lines fromthe PIC.RB7 FSEL2, Selects sampling rate for de-emphasis.Static low for 44.1K.RB6 FSEL1, Selects sampling rate for de-emphasis.Static low for 44.1K.RB5 IW2N, Selects input word length. Static high for16 bits.RB4 MDT, Serial data input for
12、 volume control. Burstat switch-on for setting to full.RB3 RSTN, Reset line. Short pulse low at switch on,then static high.RB2 MLEN, Serial data latch input for volumecontrol.RB1 MCK, Serial clock input for volume control.RB0 Not connected.No Dither On SilenceThe digital filter adds dither to the ou
13、tput signal.This improves the low-level performance of the DAC.The PWM filter normally mutes when it detectsdigital silence to prevent any unwanted noise andidle-tones on the audio outputs when no music isplaying. A slight click is audible when this happens.Unfortunately, the added dither prevents t
14、his mutefrom operating because it holds it open. Q11 detectsdigital silence on the data input to the filter. Whensilence is detected, the dither function is switched offRadioFans.CN 收音机爱 好者资料库ALPHA 7/8/9 CD SERVICE MANUALALPHA 7/8/9 CD SERVICE MANUAL16.9344MHz Low-Jitter System Clock, X1, Q5 & Z13SM
15、5843AP1 Digital Filter, Z1474HC74 Latches, Z7 & Z8SM5864 PWM Noise Shaper, Z12Analogue Filter, Z1, Z2, Z3, Z4Sony Format Digital AudioControl from PIC micro (Z211) on main pcbAudio outClockBlock Diagram of Alpha 8 DAC PCBallowing the PWM filters mute to operate as normal.Mute RelayThe mute relay is
16、controlled from the PIC micro viaRA0 after switch-on. In Standby mode, XRST is lowwhich interrupts the relay via Q9. RA0 is low whenthe CD player comes out of standby mode and goeshigh after a short settling delay.The power rail, RLYPWR, is un-regulated and has asmall reservoir capacitor (on the mot
17、her board) sothat the relay is released very soon after the mains isdisconnected from the CD player before the otherpower supply rails collapse.PWM noise shaperTo reduce EMC, the clock signal going into this chip,Z12, is very weak on the XTI pin (23) pin, takendirectly off Q5. This is amplified so t
18、hat there shouldbe a larger signal on the CKO pin (26).The PWM output on pins 11, 13, 16 and 18 can beresolved into an audio waveform on a scope simplyby measuring them through a 100K resistor. Thesame is true for the PWM signals through the latchand the level shifter.LatchThe PWM data from Z12 is r
19、e-latched using 74HC74latches, Z7 and Z8.The power supply for these chipsis the DAC voltage reference and the output drivesthe analogue filter stage directly. The latches reduceany edge-timing jitter induced on the PWM signal coming from Z12.Analogue filterThe first half of the analogue filter, Z3 a
20、nd Z4 isbalanced. The signal through one side of the op-amp,pin 1, should be phase inverted with respect to theother, pin 7. These signals should be viewed on ascope through a 100K resistor since there may stillbe quite a lot of RF noise on the signal.Z1 and Z2 filter the audio signal further and al
21、soconvert the balanced signal into a single endedsignal. Z18 acts as a DC servo to reduce the outputoffset voltage. This has a very large time constant soan offset as high as 50mV is possible when the unitis first plugged in. This reduces to less than 3mVafter 10 minutes and stays low if the unit is
22、 switchedoff and on with the Standby button.RadioFans.CN 收音机爱 好者资料库ALPHA 7/8/9 CD SERVICE MANUALALPHA 7/8/9 CD SERVICE MANUALTest Points Marked on Circuit Diagram OnlyTest PointsMeasurement Information17MHzClock Output to mother board. 16.9344MHz +/- 40ppm, 4V to 5V peak to peak square wave.AGNDAnal
23、ogue ground point.AMUTEDigital audio mute input on SK203. 0V=off, 5V=Mute.CKSerial Data clock input on SK203. Sony format.DASerial Data data input on SK203. Sony format.CLKSYNCCrystal clock override. A 16.9344MHz HCMOS clock can be injected from an external source.DEEMDe-emphasis select input on SK2
24、03. 0V=off, 5V=On.DGNDDigital ground point.LOUTLeft channel audio output at SK1. Measure d.c. offset at switch-on and after 1 minute, see specifications.LRSerial Data LR input on SK203. Sony format.MUTERLYMute Relay Voltage. Equal to RLYPWR voltage when output is muted and 0V d.c. +0.5V,-0.0V whenou
25、tput is un-muted.N15Regulated analogue supply. -15V d.c. +/- 0.6V.N18V-18.45V d.c. +/- 0.5V supply input on SK204 for analogue.P5V(0)+5V d.c. +/- 0.3V digital filter supply input on SK204. P5V(1)+5V d.c. +/- 0.3V PWM noise shaper supply input on SK204.P5VCLKRegulated clock supply. +5V d.c. +/- 0.3V.
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