LG-HT353SD-sur-sm 电路图 维修手册.pdf

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1、MODEL: HT303SU(SH33SU-S/W)/HT353SD(SH33SD-S/W)SERVICE MANUAL P/NO : AFN33723386 JANUARY, 2008 DVD/CD RECEIVER SERVICE MANUAL MODEL: HT303SU(SH33SU-S, SH33SU-W)/ HT353SD(SH33SD-S, SH33SD-W) Website Internal Use Only HT303SUHT353SD RadioFans.CN 收音机爱 好者资料库 1-1 Copyright 2008 LG Electronics.Inc.All righ

2、t reserved. Only for training and service purposes LGE Internal Use Only CONTENTS SECTION 1. GENERAL SERVICING PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 ESD PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3、 . . . . . . . . . . . . . . . . . . . 1-4 SERVICE INFORMATION FOR EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 HOW TO UPDATE AUDIO MICOM 10 F 10 F 1800 pF 1800 pF 100 k 100 k 100 100 AIN6BRight Analog Input 6 MICBIAS AGND 0.1 F * * * * * * * * * * * * NC NC N

4、C NC NC TSTI TSTO TSTO TSTO 10 F +3.3V to +5V 0.1 F10 F 0.1 F VAVD +3.3V to +5V RL See Note 2 Note 2 The value of RL is dictated by the microphone carteridge. 4. IC201 ADC(CS5345) BLOCK DIAGRAM Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes LGE Internal

5、Use Only 2-40 AIN1A AIN1B 11 12 Stereo Analog Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. AGND13Analog Ground (Input) - Ground reference for the internal analog section. VA14Analog Power (Input) - Positive power for the internal analog s

6、ection. AFILTA15Antialias Filter Connection (Output) - Antialias filter connection for the channel A ADC input. AFILTB16Antialias Filter Connection (Output) - Antialias filter connection for the channel B ADC input. VQ17Quiescent Voltage (Output) - Filter connection for the internal quiescent refere

7、nce voltage. TSTO18Test Pin (Output) - This pin must be left unconnected. FILT+19Positiv e Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. TSTO20Test Pin - This pin must be left unconnected. AIN4A/MICIN1 AIN4B/MICIN2 21 22 Stereo Analog Input 4 / Microphon

8、e Input 1 CS is the chip-select signal for SPI format. AD1/CDIN4 Addre ss Bit 1 (IC) / Ser ial Control Data Input (SPI) (Input) - AD1 is a chip address pin in IC Mode; CDIN is the input data line for the control port interface in SPI Mode. VLC5 Control Port Power (Input) - Determines the required si

9、gnal level for the control port interface. Refer to the Recommended Operating Conditions for appropriate voltages. RESET6Reset (Input) - The device enters a low-power mode when this pin is driven low. AIN3A AIN3B 7 8 Stereo Analog Input 3 (Input) - The full-scale level is specified in the ADC Analog

10、 Characteristics specification table. AIN2A AIN2B 9 10 Stereo Analog Input 2 (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. PIN DESCRIPTION Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes LGE Internal Us

11、e Only 2-41 5. IC704 PWM PIN CONFIGURATION BLOCK DIAGRAM PLL PWM Modulator Internal Controls MLRCK MBCK MSDIN0:3 SCK/SCL SO/SDA SI/I2C_AD0 /CS/I2C_AD2 PWM2_P/M PWM3_P/M PWM4_P/M PWM5_P/M PWM6_P/M /RESET OVERLOAD EXT_MUTE PWM1_P/M PWM8_P/M Internal Clock SPI/I2C PWM7_P/M SLRCK SBCK SSDIN0:3 PWM_HP_R_

12、P/M PWM_HP_L_P/M EPD_ENA PWM_SWL_P/M MIC_LRCK MIC_BCK MIC_SDIN MIC_MCLK DMIX_MCLK OLRCK OBCK DMIX_SDOUT PLL_DVDD PLL_DVSS PLL_AVDD PLL_AVSS DVDD DVSS IO_VDD IO_VSS Power Supply Reset & Power Down Internal Reset Serial Audio Output interface Automatic Gain Limiter Main Volume Trim Volume Bass Manager

13、 EQ Down Mixer Mixer Mic. Input Processor Input Mapper Sample Rate Converter Input & Output MUX Host Interface (I2C, SPI) Serial Audio Output interface Output Mapper POP NR Crystal Oscillator XIN XOUT IO_VDD PLL_DVDD IO_VSS IO_VSS PLL_AVDD IO_VSS PLL_AVSS PLL_DVSS MLRCK MBCK MSDIN0 MIC_LRCK MIC_BCK

14、MIC_MCLK PWM_HP_R_P IO_VSS PWM2_P PWM2_M PWM3_P PWM3_M PWM4_P PWM4_M SPI/I2C /CS/I2C_AD2 SI/I2C_AD0 SO/SDA SCK/SCL /RESET SCAN_ENA XIN DVSS IO_VSS IO_VSS IO_VSS DVDD DVSS IO_VDD IO_VSS MSDIN1 MSDIN2 SLRCK SBCK DVSS PWM5_P PWM5_M DVDD TEST_MODE3 DVSS IO_VSS PWM6_P PWM6_M IO_VSS IO_VSS PWM1_P PWM1_M O

15、VERLOAD IO_VSS IO_VSS SSDIN1 EXT_MUTE DVDD IO_VDD DVDD SSDIN0 MSDIN3 SSDIN2 SSDIN3 IO_VSS IO_VDD MIC_SDIN PWM_SWL_P PWM_SWL_M PWM_HP_L_P PWM_HP_L_M PWM_HP_R_M IO_VSS PWM7_P PWM7_M PWM8_P PWM8_M EPD_ENA TEST_MODE2 TEST_MODE1 IO_VSS DMIX_LRCK DMIX_BCK DMIX_SDOUT DMIX_MCLK 98 99 100 96 97 93 94 95 91 9

16、2 85 86 87 88 89 90 83 84 81 82 71 72 73 74 75 61 62 63 64 65 66 67 68 69 70 53 54 55 56 57 58 59 51 52 60 46 47 48 49 50 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 30 31 32 33 34 35 36 37 26 27 28 29 76 77 78 79 80 17 18 19 20 38 39 40 41 42 43 44 45 21 22 23 24 25 IO_VDD IO_VSS IO_VDD DVDD DVSS IO_VDD

17、 IO_VDD IO_VDD DVSS DVDD IO_VDD PULSUS XOUT Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes LGE Internal Use Only 2-42 5. IC704 PWM PIN DESCRIPTION NamePin NO. Type Description Power and Ground PLL_AVDD 6 Analog Power PLL analog power supply. PLL_AVSS 8 A

18、nalog Ground PLL analog ground. PLL_DVDD 3 PLL Power PLL digital power supply. PLL_DVSS 2 PLL Ground PLL digital ground. DVDD 13, 34, 42, 66, 80, 91 Power Core power supply. DVSS 14, 35, 43, 63, 81, 92 GroundCore digital ground. IO_VDD 4, 10, 22, 29, 39, 47, 56, 65, 72, 94 Power I/O power supply. 3.

19、3V Digital power supply. IO_VSS 1, 5, 7, 9, 21, 28, 38, 44, 50, 53, 57, 60, 64, 69, 73, 85, 95 GroundI/O digital ground. Reset and Clock /RESET 96 I H/W reset signal. Active Low Schmitt-Trigger input. The Schmitt-Trigger input allows a slowly rising input to reset the chip reliably. The RESET signal

20、 must be asserted Low during power up. De-assert High for normal operation. XIN 86 Analog Crystal Oscillator input pin. XOUT 87 Analog Crystal Oscillator output pin. PCM Audio Input/Output Interface MBCK 11 I/O PCM bit clock input/output of main 8-channel audio. User can select the master/slave mode

21、 of this signal. Schmitt-Trigger input. MLRCK 12 I/O PCM Word clock (left-right clock) input/output of main 8-channel audio. User can select the master/slave mode of this signal. Schmitt-Trigger input. MSDIN 3:0 15, 16, 17, 18 I PCM serial data input of main 8-channel audio. Schmitt-Trigger input. S

22、BCK 19 I/O PCM bit clock input/output of 8-channel audio. User can select the master/slave mode of this signal. Schmitt-Trigger input. SLRCK 20 I/O PCM word clock (left-right clock) input/output of sub 8-channel audio. User can select the master/slave mode of this signal. Schmitt-Trigger input. SSDI

23、N 3:0 23, 24, 25, 26 I/O PCM serial data input of sub-channel audio. User can set this sub-channel data input pins to PCM serial data output pins. See the Control Register Description part. Schmitt-Trigger input Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purp

24、oses LGE Internal Use Only 2-43 MIC_MCLK 30 O Main clock for external microphone input A/DC. Clock frequency can be selected between 6.144MHz, 12.288MHz, and 24.576MHz. MIC_BCK 31 I/O PCM bit clock input/output of external microphone. Bit clock frequency is 3.072MHz (48kHz x 64, fixed) MIC_LRCK 32 I

25、/O PCM Word clock (left-right clock) input/output of external microphone. Word clock rate is 48kHz (fixed). MIC_SDIN 33 I PCM serial data input of external microphone. Schmitt-Trigger input. DMIX_MCLK 93 O Main clock for external down-mix line output D/AC. DMIX_BCK 89 O PCM bit clock output of down-

26、mix signal. Bit clock frequency is 6.144MHz (96kHz x 64, fixed) DMIX_LRCK 88 O PCM Word clock (left-right clock) output of down-mix signal. Word clock rate is 96kHz (fixed). DMIX_SDOUT 90 O PCM serial data output of down-mix signal. PWM Audio Output PWM1_P 49 O Positive PWM output of channel 1. PWM1

27、_M 48 O Negative PWM output of channel 1. PWM2_P 52 O Positive PWM output of channel 2. PWM2_M 51 O Negative PWM output of channel 2. PWM3_P 55 O Positive PWM output of channel 3. PWM3_M 54 O Negative PWM output of channel 3. PWM4_P 59 O Positive PWM output of channel 4. PWM4_M 58 O Negative PWM out

28、put of channel 4. PWM5_P 62 O Positive PWM output of channel 5. PWM5_M 61 O Negative PWM output of channel 5. PWM6_P 68 O Positive PWM output of channel 6. PWM6_M 67 O Negative PWM output of channel 6. PWM7_P 71 O Positive PWM output of channel 7. PWM7_M 70 O Negative PWM output of channel 7. PWM8_P

29、 75 O Positive PWM output of channel 8. PWM8_M 74 O Negative PWM output of channel 8. PWM_HP_L_P 46 O Positive PWM output of headphone left channel. PWM_HP_L_M 45 O Negative PWM output of headphone left channel. PWM_HP_R_P 41 O Positive PWM output of headphone right channel. PWM_HP_R_M 40 O Negative

30、 PWM output of headphone right channel. PWM_SWL_P 37 O Positive PWM output of subwoofer line output. PWM_SWL_M 36 O Negative PWM output of subwoofer line output. System Control Interface SPI/I2C 84 I Host interface mode (SPI or I2C) selector. Assert HIGH for SPI mode. De-assert LOW for I2C mode. Int

31、ernal pull-down resistor. SO/SDA 78 I/O SO for SPI mode or SDA for I2C mode. Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes LGE Internal Use Only 2-44 SCK/SCL 79 I SCK for SPI mode or SCL for I2C mode. Schmitt-Trigger input. SI/I2C_AD0 82 I SI for SPI mo

32、de or Slave Address 0 for I2C mode. Schmitt-Trigger input. Internal pull-down resistor. /CS/I2C_AD2 83 I Chip selector (CS) for SPI mode or Slave Address 2 for I2C mode. Schmitt-Trigger input. Internal pull-down resistor. Special Control Interface EXT_MUTE 27 I External mute control input. Active Hi

33、gh. Assert HIGH to mute audio output. Internal pull-down resistor. OVERLOAD 76 I Power stage overload indication input. Polarity is programmable. Schmitt-Trigger input. When OVERLOAD is asserted, all PWM audio outputs go to “LOW”. That shutdown process is programmable. Internal pull-down resistor. E

34、PD_ENA 77 O External amplifier power device enable output. Active High. Test Mode TEST_MODE1 97 I Test mode selection pin 1. In normal operation, it should be “LOW” or not connected. Internal pull-down resistor. TEST_MODE2 98 I Test mode selection pin 2. In normal operation, it should be “LOW” or no

35、t connected. Internal pull-down resistor. SCAN_ENA 99 I Scan enable. Active High. In normal operation, it should be “LOW” or not connected. Internal pull-down resistor. TEST_MODE3 100 I Test mode selection pin 3. In normal operation, it should be “LOW” or not connected. Internal pull-down resistor.

36、All inputs and bi-directional inputs are 5 Volt tolerant. The corresponding pins can be connected to the buses that can swing between 0V and 5V. The output-only pins are not 5V tolerant and the buses they are connected to can swing only between 0V and 3.3V. Copyright 2008 LG Electronics.Inc.All righ

37、t reserved. Only for training and service purposes LGE Internal Use Only2-452-46 WIRING DIAGRAM 2007. 11. 30 PN202 CABLE1 Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes LGE Internal Use Only2-472-48 OVERALL BLOCK DIAGRAM 2007. 11. 30 Copyright 2008 LG El

38、ectronics.Inc.All right reserved. Only for training and service purposes LGE Internal Use Only 2007. 11. 30 A 1 2 3 4 5 6 7 8 9 10 11 12 BCDEFGHIJKLMNOPQRST NOTES) Symbol denotes DC chassis ground. NOTE) Warning NOTE) Parts that are shaded are critical NOTE) With respect to risk of fire or NOTE) ele

39、ctricial shock. 2-492-50 CIRCUIT DIAGRAMS 1. SMPS(POWER) CIRCUIT DIAGRAM IMPORTANT SAFETY NOTICE WHEN SERVICING THIS CHASSIS, UNDER NO CIR- CUMSTANCES SHOULD THE ORIGINAL DESIGN BE MODIFIED OR ALTERED WITHOUT PERMISSION FROM THE LG CORPORATION. ALL COMPONENTS SHOULD BE REPLACED ONLY WITH TYPES IDENT

40、I- CAL TO THOSE IN THE ORIGINAL CIRCUIT. SPECIAL COMPONENTS ARE SHADED ON THE SCHEMATIC FOR EASY IDENTIFICATION. THIS CIRCUIT DIAGRAM MAY OCCASIONALLY DIF- FER FROM THE ACTUAL CIRCUIT USED. THIS WAY, IMPLEMENTATION OF THE LATEST SAFETY AND PERFORMANCE IMPROVEMENT CHANGES INTO THE SET IS NOT DELAYED

41、UNTIL THE NEW SERVICE LITERATURE IS PRINTED. NOTE : 1. Shaded() parts are critical for safety. Replace only with specified part number. 2. Voltages are DC-measured with a digital voltmeter during Play mode. Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes

42、LGE Internal Use Only2-512-52 2. MPEG CIRCUIT DIAGRAM 2007. 11. 30 A 1 2 3 4 5 6 7 8 9 10 11 12 BCDEFGHIJKLMNOPQRST Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes LGE Internal Use Only2-532-54 3. SERVO CIRCUIT DIAGRAM 2007. 11. 30 A 1 2 3 4 5 6 7 8 9 10

43、11 12 BCDEFGHIJKLMNOPQRST Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes LGE Internal Use Only2-552-56 4. MICOM CIRCUIT DIAGRAM 2007. 11. 30 A 1 2 3 4 5 6 7 8 9 10 11 12 BCDEFGHIJKLMNOPQRST Copyright 2008 LG Electronics.Inc.All right reserved. Only for t

44、raining and service purposes LGE Internal Use Only2-572-58 5. I/O CIRCUIT DIAGRAM 2007. 11. 30 A 1 2 3 4 5 6 7 8 9 10 11 12 BCDEFGHIJKLMNOPQRST Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes LGE Internal Use Only2-592-60 6. AMP CIRCUIT DIAGRAM 2007. 11.

45、30 A 1 2 3 4 5 6 7 8 9 10 11 12 BCDEFGHIJKLMNOPQRST Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes LGE Internal Use Only2-612-62 7. MIC CIRCUIT DIAGRAM 2007. 11. 30 A 1 2 3 4 5 6 7 8 9 10 11 12 BCDEFGHIJKLMNOPQRST Copyright 2008 LG Electronics.Inc.All ri

46、ght reserved. Only for training and service purposes LGE Internal Use Only2-632-64 8. FRONT CIRCUIT DIAGRAM 2007. 11. 30 A 1 2 3 4 5 6 7 8 9 10 11 12 BCDEFGHIJKLMNOPQRST 2-652-66 9. PWR KEY CIRCUIT DIAGRAM Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes L

47、GE Internal Use Only 2007. 11. 30 A 1 2 3 4 5 6 7 8 9 10 11 12 BCDEFGHIJKLMNOPQRST 2-672-68 10. MIC & USB & PTB CIRCUIT DIAGRAM 2007. 11. 30 A 1 2 3 4 5 6 7 8 9 10 11 12 BCDEFGHIJKLMNOPQRST Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes LGE Internal Use

48、Only Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes LGE Internal Use Only2-692-70 PRINTED CIRCUIT BOARD DIAGRAMS 1. MAIN P.C. BOARD DIAGRAM ( TOP VIEW ) Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes LGE Inte

49、rnal Use Only2-712-72 MAIN P.C. BOARD DIAGRAM ( BOTTOM VIEW ) Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes LGE Internal Use Only2-732-74 2. SMPS P.C. BOARD DIAGRAM NOTE:Warning Parts that are shaded are critical With respect to risk of fire or electrical shock. Copyright 2008 LG Electronics.Inc.All right reserved. Only for training and service purposes LGE Internal Use Only TIMER P.C BOARD DIA