AD9958.PDF

《AD9958.PDF》由会员分享，可在线阅读，更多相关《AD9958.PDF（40页珍藏版）》请在收音机爱好者资料库上搜索。

1、 2-Channel 500 MSPS DDS with 10-Bit DACs AD9958 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its

2、use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.

3、S.A. Tel: 781.329.4700 Fax: 781.461.3113 2005 Analog Devices, Inc. All rights reserved. FEATURES 2 synchronized DDS channels 500 MSPS Independent frequency/phase/amplitude control between channels Matched latencies for frequency/phase/amplitude changes Excellent channel-to-channel isolation (72 dB)

4、Linear frequency/phase/amplitude sweeping capability Up to 16 levels of frequency/phase/amplitude modulation (pin-selectable) 2 integrated 10-bit D/A converters (DACs) Individually programmable DAC full-scale currents 32-bit frequency tuning resolution 14-bit phase offset resolution 10-bit output am

5、plitude scaling resolution Serial I/O Port (SPI) with 800Mbps data throughput Software-/hardware-controlled power-down Dual supply operation (1.8 V DDS core/3.3 V serial I/O) Multiple device synchronization Selectable 4 to 20 REF_CLK multiplier (PLL) Selectable REF_CLK crystal oscillator 56-Lead LFC

6、SP APPLICATIONS Agile local oscillator Phased array radar/sonar Instrumentation Synchronized clocking RF source for AOTF Single-side band suppressed carrier Quadrature communications FUNCTIONAL BLOCK DIAGRAM AD9958 32321015 IOUT 10 DAC COS(X) DDS CORE IOUT 32 FTW FTW SYNC_CLK CLK_MODE_SEL BUFFER/ XT

7、AL OSCILLATOR SYSTEM CLK 1.8V AVDDDVDD SYNC_IN SYNC_OUT I/O_UPDATE 32 32PHASE/ PHASE AMP/ AMP 1014 1015 IOUT 10 DAC IOUT DAC_RSET REF_CLK REF_CLK PWR_DWN_CTL MASTER_RESET SCLK SDIO_0 SDIO_1 SDIO_2 SDIO_3 CS TIMING AND CONTROL LOGIC SCALABLE DAC REF CURRENT MUX I/O PORT BUFFER CONTROL REGISTERS CHANN

8、EL REGISTERS PROFILE REGISTERS 4 REF CLOCK MULTIPLIER 4 TO 20 1.8V PS0 PS1 PS2 PS3DVDD_I/O COS(X) DDS CORE 05252-001 Figure 1. AD9958 Rev. 0 | Page 2 of 40 TABLE OF CONTENTS Features.1 Applications.1 Functional Block Diagram.1 General Description.3 Specifications.4 Absolute Maximum Ratings.8 ESD Cau

9、tion.8 Equivalent Input and Output Circuits.8 Pin Configuration and Function Descriptions.9 Typical Performance Characteristics.11 Application Circuits.14 Theory of Operation.17 DDS Core.17 D/A Converter.17 Modes of Operation.18 Channel Constraint Guidelines.18 Power Supplies.18 Single-Tone Mode .18

10、 Reference Clock Modes.19 Scalable DAC Reference Current Control Mode.20 Power-Down Functions.20 Modulation Mode.20 Modulation Using SDIO Pins for RU/RD.22 Linear Sweep (Shaped) Modulation Mode.22 Linear SweepNo-Dwell Mode.24 Sweep and Phase Accumulator Clearing Functions. 25 Output Amplitude Contro

11、l Mode. 26 Synchronizing Multiple AD9958 Devices. 27 Automatic Mode Synchronization. 27 Manual Software Mode Synchronization. 27 Manual Hardware Mode Synchronization. 27 I/O_Update, SYNC_CLK, and System Clock Relationships 28 Serial I/O Port. 29 Overview . 29 Instruction Byte Description. 30 Serial

12、I/O Port Pin Description. 30 Serial I/O Port Function Description. 30 MSB/LSB Transfer Description. 30 Serial I/O Modes of Operation. 31 Register Maps. 34 Control Register Map . 34 Channel Register Map. 35 Profile Register Map. 35 Control Register Descriptions. 36 Channel Select Register (CSR) . 36

13、Channel Function Register (CFR) Description. 37 Outline Dimensions. 39 Ordering Guide . 39 REVISION HISTORY 9/05Revision 0: Initial Version AD9958 Rev. 0 | Page 3 of 40 GENERAL DESCRIPTION The AD9958 consists of two DDS cores that provide indepen- dent frequency, phase, and amplitude control on each

14、 channel. This flexibility can be used to correct imbalances between signals due to analog processing such as filtering, amplification, or PCB layout related mismatches. Since both channels share a common system clock, they are inherently synchronized. Synchronization of multiple devices is supporte

15、d. The AD9958 can perform up to a 16-level modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. In addition, the AD9958 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentati

16、on. The AD9958 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers an SPI- compatible mode of operation that is virtually identical to the SPI operation found in earlier Analog Devices DDS products. Flexibility is provided by four data pins (

17、SDIO_0:3) that allow four programmable modes of serial I/O operation. The AD9958 uses advanced DDS technology that provides low power dissipation with high performance. The device incorporates two integrated, high speed 10-bit DACs with excellent wideband and narrowband SFDR. Each channel has a dedi

18、cated 32-bit frequency tuning word, 14 bits of phase offset, and a 10-bit output scale multiplier. The DAC outputs are supply referenced and must be termin- ated into AVDD by a resistor or an AVDD center-tapped transformer. Each DAC has its own programmable reference to enable different full-scale c

19、urrents for each channel. The DDS acts as a high resolution frequency divider with the REF_CLK as the input and the DAC providing the output. The REF_CLK input source is common to both channels and can be driven directly or used in combination with an integrated REF_CLK multiplier (PLL) up to a maxi

20、mum of 500 MSPS. The PLL multiplication factor is programmable from 4 to 20, in integer steps. The REF_CLK input also features an oscillator circuit to support an external crystal as the REF_CLK source. The crystal must be between 20 MHz and 30 MHz. The crystal can be used in combination with the RE

21、F_CLK multiplier. The AD9958 comes in a space-saving 56-lead LFCSP package. The DDS core (AVDD and DVDD pins) is powered by a 1.8 V supply. The digital I/O interface (SPI) operates at 3.3 V and requires the pin labeled DVDD_I/O (Pin 49) be connected to 3.3 V. The AD9958 operates over the industrial

22、temperature range of 40C to +85C. AD9958 Rev. 0 | Page 4 of 40 SPECIFICATIONS AVDD and DVDD = 1.8 V 5%; DVDD_I/O = 3.3 V 5%; RSET = 1.91 k; external reference clock frequency = 500 MSPS (REF_CLK multiplier bypassed), unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comment

23、s REF CLOCK INPUT CHARACTERISTICS See Figure 33 and Figure 34 Frequency Range REF_CLK Multiplier Bypassed 1 500 MHz REF_CLK Multiplier Enabled 10 125 MHz Internal VCO Output Frequency Range VCO Gain Bit Set High1 255 500 MHz Internal VCO Output Frequency Range VCO Gain Bit Set Low1 100 160 MHz Cryst

24、al REF_CLK Source Range 20 30 MHz Input Power Sensitivity 5 3 dBm Measured at the pin (single-ended) Input Voltage Bias Level 1.15 V Input Capacitance 2 pF Input Impedance 1500 Duty Cycle w/REF_CLK Multiplier Bypassed 45 55 % Duty Cycle w/REF_CLK Multiplier Enabled 35 65 % CLK Mode Select (Pin 24) L

25、ogic 1 Voltage 1.25 1.8 V 1.8V digital input logic CLK Mode Select (Pin 24) Logic 0 Voltage 0.5 V 1.8 V digital input logic DAC OUTPUT CHARACTERISTICS Must be referenced to AVDD Resolution 10 Bits Full-Scale Output Current 1.25 10 mA Gain Error 10 10 %FS Channel-to-Channel Output Amplitude Matching

26、Error 2.5 2.5 % Output Current Offset 1 25 A Differential Nonlinearity 0.5 LSB Integral Nonlinearity 1.0 LSB Output Capacitance 3 pF Voltage Compliance Range AVDD 0.50 AVDD + 0.50 V Channel-to-Channel Isolation 72 dB DAC supplies tied together (see Figure 21) WIDEBAND SFDR The frequency range for wi

27、deband SFDR is defined as dc to Nyquist 1 to 20 MHz Analog Out 65 dBc 20 to 60 MHz Analog Out 62 dBc 60 to 100 MHz Analog Out 59 dBc 100 to 150 MHz Analog Out 56 dBc 150 to 200 MHz Analog Out 53 dBc NARROWBAND SFDR 1.1 MHz Analog Out (10 kHz) 90 dBc 1.1 MHz Analog Out (50 kHz) 88 dBc 1.1 MHz Analog

28、Out (250 kHz) 86 dBc 1.1 MHz Analog Out (1 MHz) 85 dBc 15.1 MHz Analog Out (10 kHz) 90 dBc 15.1 MHz Analog Out (50 kHz) 87 dBc 15.1 MHz Analog Out (250 kHz) 85 dBc 15.1 MHz Analog Out (1 MHz) 83 dBc 40.1 MHz Analog Out (10 kHz) 90 dBc 40.1 MHz Analog Out (50 kHz) 87 dBc 40.1 MHz Analog Out (250 kHz)

29、 84 dBc 40.1 MHz Analog Out (1 MHz) 82 dBc 75.1 MHz Analog Out (10 kHz) 87 dBc AD9958 Rev. 0 | Page 5 of 40 Parameter Min Typ Max Unit Test Conditions/Comments 75.1 MHz Analog Out (50 kHz) 85 dBc 75.1 MHz Analog Out (250 kHz) 83 dBc 75.1 MHz Analog Out (1 MHz) 82 dBc 100.3 MHz Analog Out (10 kHz) 87

30、 dBc 100.3 MHz Analog Out (50 kHz) 85 dBc 100.3 MHz Analog Out (250 kHz) 83 dBc 100.3 MHz Analog Out (1 MHz) 81 dBc 200.3 MHz Analog Out (10 kHz) 87 dBc 200.3 MHz Analog Out (50 kHz) 85 dBc 200.3 MHz Analog Out (250 kHz) 83 dBc 200.3 MHz Analog Out (1 MHz) 81 dBc PHASE NOISE CHARACTERISTICS Residual

31、 Phase Noise 15.1 MHz (fOUT) 1 kHz Offset 150 dBc/Hz 10 kHz Offset 159 dBc/Hz 100 kHz Offset 165 dBc/Hz 1 MHz Offset 165 dBc/Hz Residual Phase Noise 40.1 MHz (fOUT) 1 kHz Offset 142 dBc/Hz 10 kHz Offset 151 dBc/Hz 100 kHz Offset 160 dBc/Hz 1 MHz Offset 162 dBc/Hz Residual Phase Noise 75.1 MHz (fOUT)

32、 1 kHz Offset 135 dBc/Hz 10 kHz Offset 146 dBc/Hz 100 kHz Offset 154 dBc/Hz 1 MHz Offset 157 dBc/Hz Residual Phase Noise 100.3 MHz (fOUT) 1 kHz Offset 134 dBc/Hz 10 kHz Offset 144 dBc/Hz 100 kHz Offset 152 dBc/Hz 1 MHz Offset 154 dBc/Hz Residual Phase Noise 15.1 MHz (fOUT) w/REF_CLK Multiplier Enabl

33、ed 5 1 kHz Offset 139 dBc/Hz 10 kHz Offset 149 dBc/Hz 100 kHz Offset 153 dBc/Hz 1 MHz Offset 148 dBc/Hz Residual Phase Noise 40.1 MHz (fOUT) w/REF_CLK Multiplier Enabled 5 1 kHz Offset 130 dBc/Hz 10 kHz Offset 140 dBc/Hz 100 kHz Offset 145 dBc/Hz 1 MHz Offset 139 dBc/Hz Residual Phase Noise 75.1 MHz

34、 (fOUT) w/REF_CLK Multiplier Enabled 5 1 kHz Offset 123 dBc/Hz 10 kHz Offset 134 dBc/Hz 100 kHz Offset 138 dBc/Hz 1 MHz Offset 132 dBc/Hz Residual Phase Noise 100.3 MHz (fOUT) w/REF_CLK Multiplier Enabled 5 1 kHz Offset 120 dBc/Hz 10 kHz Offset 130 dBc/Hz 100 kHz Offset 135 dBc/Hz 1 MHz Offset 129 d

35、Bc/Hz AD9958 Rev. 0 | Page 6 of 40 Parameter Min Typ Max Unit Test Conditions/Comments Residual Phase Noise 15.1 MHz (fOUT) w/REF_CLK Multiplier Enabled 20 1 kHz Offset 127 dBc/Hz 10 kHz Offset 136 dBc/Hz 100 kHz Offset 139 dBc/Hz 1 MHz Offset 138 dBc/Hz Residual Phase Noise 40.1 MHz (fOUT) w/REF_CL

36、K Multiplier Enabled 20 1 kHz Offset 117 dBc/Hz 10 kHz Offset 128 dBc/Hz 100 kHz Offset 132 dBc/Hz 1 MHz Offset 130 dBc/Hz Residual Phase Noise 75.1 MHz (fOUT) w/REF_CLK Multiplier Enabled 20 1 kHz Offset 110 dBc/Hz 10 kHz Offset 121 dBc/Hz 100 kHz Offset 125 dBc/Hz 1 MHz Offset 123 dBc/Hz Residual

37、Phase Noise 100.3 MHz (fOUT) w/REF_CLK Multiplier Enabled 20 1 kHz Offset 107 dBc/Hz 10 kHz Offset 119 dBc/Hz 100 kHz Offset 121 dBc/Hz 1 MHz Offset 119 dBc/Hz SERIAL PORT TIMING CHARACTERISTICS Maximum Frequency Serial Clock (SCLK) 200 MHz Minimum SCLK Pulse Width Low (tPWL) 1.6 ns Minimum SCLK Pul

38、se Width High (tPWH) 2.2 ns Minimum Data Set-Up Time (tDS) 2.2 ns Minimum Data Hold Time 0 ns Minimum CSB Set-Up Time (tPRE) 1.0 ns Minimum Data Valid Time for Read Operation 12 ns MISCELLANEOUS TIMING CHARACTERISTICS Master_Reset Minimum Pulse Width 1 Min pulse width = 1 sync clock period I/O_Updat

39、e Minimum Pulse Width 1 Min pulse width = 1 sync clock period Minimum Set-Up Time (I/O_Update to SYNC_CLK) 4.8 ns Rising edge to rising edge Minimum Hold Time (I/O_Update to SYNC_CLK) 0 ns Rising edge to rising edge Minimum Set-Up Time (Profile Inputs to SYNC_CLK) 5.4 ns Minimum Hold Time (Profile Inputs to SYNC_CLK) 0 ns Minimum Set-Up Time (SDIO Inputs to SYNC_CLK) 2.5 ns Minimum Hold Time (SDIO Inputs to SYNC_CLK) 0 ns Propagation Time Between REF_CLK and SYNC_CLK 2.25 3.5 5.5 ns CMOS LOGIC INPUTS VIH 2.0