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1、D supports TMDS logic level. 48 TXC+ Output Differential Clock Output. Differential clock output at the TMDS clock rate; supports TMDS logic level. RadioFans.CN 82 Location Mnemonic Type Description 49 TXGND Ground TXAVDD Ground 50 TX0- HDMI Output Differential Output Channel 0 Complement. Different
2、ial output of the red data at 10 the pixel clock rate; supports TMDS logic level. 51 TX0+ HDMI Output Differential Output Channel 0 True. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 52 TXGND Ground TXAVDD Ground 53 TX1- HDMI Output Differential Output C
3、hannel 1 Complement. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 54 TX1+ HDMI Output Differential Output Channel 1 True. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 55 TXAVDD Power 1.8V power supply for TMD
4、S outputs 56 TX2- HDMI Output Differential Output Channel 2 Complement. Differential output of the red data at 10 the pixel clock rate; supports TMDS logic level. 57 TX2+ HDMI Output Differential Output Channel 2 True. Differential output of the red data at 10 the pixel clock rate; supports TMDS log
5、ic level. 58 TXGND Ground TXAVDD Ground 59 CEC Digital I/O Consumer electronic control channel. 60 DGND Ground Ground for DVDD 61 DVDD PowerDigital supply voltage (1.8 V) 62 ALSB Digital Input This pin is used to set I2C address of the Rx IO and the Tx Main Map. 63 CSB Digital Input Chip Select pin.
6、 This pin must be set low or left floating for the chip to process I2C messages that are destined to the ADV7622. The ADV7622 ignores I2C messages which he receives if this pin is high. 64 EP_SCK Digital Output SPI clock interface for the EDID 65 EP_CS Digital Output SPI chip selected interface for
7、the EDID 66 EP_MOSI Digital Output SPI master out/slave in for the EDID 67 EP_MISO Digital Input SPI master in/slave out for the EDID 68 MCLK_IN Digital Input Audio Reference Clock. 128 N fs with RadioFans.CN 83 Location Mnemonic Type Description N = 1, 2, 3, or 4. Set to 128 sampling frequency (fs)
8、, 256 fs, 384 fs, or 512 fs. Supports 1.8 V to 3.3 V CMOS logic levels. 69 SCLK_IN Digital Input I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V. 70 AP5_IN Digital Input Audio Input Port 5. CMOS logic levels from 1.8 V to 3.3 V. 71 AP4_IN Digital Input Audio Input Port 4. CMOS logic
9、levels from 1.8 V to 3.3 V. 72 DGNDIO Ground Ground for DVDDIO 73 DVDDIO Power Digital I/O supply voltage (3.3 V) 74 AP3_IN Digital Input Audio Input Port 3. CMOS logic levels from 1.8 V to 3.3 V. 75 AP2_IN Digital Input Audio Input Port 2. CMOS logic levels from 1.8 V to 3.3 V. 76 AP1_IN Digital In
10、put Audio Input Port 1. CMOS logic levels from 1.8 V to 3.3 V. 77 AP0_IN Digital Input Audio Input Port 0. CMOS logic levels from 1.8 V to 3.3 V. 78 SDATA Digital I/O I2C port serial data input/output pin. SDA is the data line for the control port. 79 SCL Digital Input I2C port serial clock input. S
11、CL is the clock line for the control port. 80 DGND Ground Ground for DVDD 81 DVDD PowerDigital supply voltage (1.8 V) 82 INT1 (AMUTE1) Digital Output Interrupt pin, can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user c
12、ontrol. This pin can also output an audio mute signal 83 INT2 (AMUTE2) Digital Output Interrupt pin, can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user control. This pin can also output an audio mute signal. I2C LSB s
13、election. 84 INT_TX Digital Output Interrupt. Open drain. A 2 k pull-up resistor to the microcontroller I/O supply is recommended. 85 DGNDIO GroundGround for DVDDIO 86 DVDDIO PowerDigital I/O supply voltage (3.3 V) RadioFans.CN 84 Location Mnemonic Type Description 87 AP0_OUT Digital Output Audio ou
14、tput port 0. 88 AP1_OUT Digital Output Audio output port 1. 89 AP2_OUT Digital Output Audio output port 2. 90 AP3_OUT Digital Output Audio output port 3. 91 AP4_OUT Digital Output Audio output port 4. 92 DGND Ground Ground for DVDD 93 DVDD PowerDigital supply voltage (1.8 V) 94 AP5_OUT Digital Outpu
15、t Audio output port 5. 95 SCLK_OUT Digital Output Audio serial clock output. 96 MCLK_OUT Digital Output Audio master clock output. 97 RESETB Digital Input System reset input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7622 circuitry. 98 PWRDNB Digital Input Activ
16、e low power-down pin. This pin should be used as a system detect when the internal EDID is powered from the 5V signal from the HDMI port when connected to active equipment. Pin pulled down internally. 99 PGND Ground Ground for PVDD 100 PVDD PowerPLL supply voltage 101 XTAL Miscellaneous Analog Input
17、 pin for 28.63636 MHz crystal or an external 1.8 V 28.63636 MHz clock oscillator source to clock the ADV7622. The following crystal frequencies are also supported: 24.576 MHz and 27 MHz. 102 XTAL1 Miscellaneous Analog Crystal output pin. This pin should be left floating if a clock oscillator is used
18、. 103 PVDD PowerPLL supply voltage 104 PGND Ground PVDD Ground 105 HP_CTRLA Digital Output Hot Plug Detect for port A. 106 5V_DETA Digital Input 5 V detect pin for port A in the HDMI interface. 107 RTERM Miscellaneous Analog Sets internal termination resistance. A 500 resistor between this pin and G
19、ND should be used. 108 DDCA_SDA Digital I/O HDCP slave serial data port A. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant. 109 DDCA_SCL Digital Input HDCP slave serial clock port A. DDCD_SCL is a 3.3 V input that is 5 V tolerant. 110 CVDD PowerReceiver comparator supply voltage (1.8V) 111 CGN
20、D Ground TVDD and CVDD Ground RadioFans.CN 85 Location Mnemonic Type Description 112 RXA_C- HDMI Input Digital input clock Complement of port A in the HDMI interface. 113 RXA_C+ HDMI Input Digital input clock True of port A in the HDMI interface. 114 TVDD Power Receiver terminator supply voltage (3.
21、3 V) 115 RXA_0- HDMI Input Digital input channel 0 complement of port A in the HDMI interface. 116 RXA_0+ HDMI Input Digital input channel 0 true of port A in the HDMI interface. 117 CGND Ground TVDD and CVDD Ground 118 RXA_1- HDMI Input Digital input channel 1 complement of port A in the HDMI inter
22、face. 119 RXA_1+ HDMI Input Digital input channel 1 true of port A in the HDMI interface. 120 TVDD Power Receiver terminator supply voltage (3.3 V) 121 RXA_2- HDMI Input Digital input channel 2 complement of port A in the HDMI interface. 122 RXA_2+ HDMI Input Digital input channel 2 true of port A i
23、n the HDMI interface. 123 HP_CTRLB Digital Output Hot Plug Detect for port B. 124 5V_DETB Digital Input 5 V detect pin for port B in the HDMI interface. 125 DGND Ground Ground for DVDD 126 DVDD PowerDigital supply voltage (1.8 V) 127 DDCB_SDA Digital I/O HDCP slave serial data ports B. DDCB_SDA is a
24、 3.3 V input/output that is 5 V tolerant. 128 DDCB_SCL Digital Input HDCP slave serial clock port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. 129 CVDD PowerReceiver comparator supply voltage (1.8V) 130 CGND Ground TVDD and CVDD Ground 131 RXB_C- HDMI Input Digital input clock complement of po
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