C.Audio-XR3801-pwr-sm维修电路原理图.pdf

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1、XR3801 Circuit Description and Service Notes Introduction These notes are intended to assist maintenance and service of the XR3801 amplifier. It is recommended that reference is made to the relevant schematic diagrams and system diagram whilst reading this document. The component references of the t

2、wo amplifier channel electronics are appended “A” and “B” respectively. Shared circuitry (such as that of the protection system) has no suffix. This document will refer to channel A references only. Operation of channel B is identical except where explicitly noted. Voltage values in bold mentioned i

3、n the text are test voltages which may be used for diagnostic purposes, although attention is drawn to the surrounding text which explains circuit operation and may qualify such measurements. Mechanical Construction The mechanical structure of the unit is made up of two identical side panels, a rear

4、 panel, and a 3mm steel structural front panel. The rear panel is fixed to the side panels by means of six M5 screws (three each side) which also secure the two rear rack mounting brackets. The front panel is fixed to the side panels by means of two side fixing brackets secured to the front by way o

5、f the handle screws and to the sides by three M5 screws each side. The main circuit board is fixed to the two heatsinks by the power device fixing screws and is spaced from the circuit board by way of insulating bushes. The circuit board/heatsink assembly is fixed to the rear and side panels by a to

6、tal of eight M5 screws. The mains transformer is supported on the internal “transformer tray” which is fixed directly to the structural front panel. The extruded cosmetic front panel is fixed directly to the structural front panel by two M5 screws. Top and bottom covers complete the assembly each fi

7、xed in place by eight M4 screws. Access to all the major components may be gained by removal of the top and bottom covers, further disassembly is rarely required. Circuit description Input Stage The input stage is built around TL071 operational amplifier IC1A, configured as a unity-gain differential

8、 amplifier. Its correct operation is dependent upon both of its input terminals being correctly terminated and, therefore, any gain errors around this stage may be a result of a fault in the screened cable connection to the input PCB P1030. Preset potentiometer VR2A adjusts the gain of this stage an

9、d thereby provides adjustment to optimise the Common-Mode-Rejection of the input stage. This preset is factory set for optimum rejection and should not be re-adjusted unless it has been necessary to change any components around the input stage. The trimming procedure is as follows : Inject a common-

10、mode test signal at 1kHz and +4dBu to the channel under test. The common-mode test signal of the Audio Precision test system is suitable, otherwise connect the signal to both pins 2 & 3 via 51 Ohm resistors. Observe the amplifier output and adjust VR2A for minimum output. Power for the input stage i

11、s derived from the main +LT supply via 1W resistors R101A and R102A and shunt regulated to a nominal +18V by D22A and D23A. The output of the input differential amplifier is fed via 1k “Build-out” resistor R57A and twin screen cable to the front panel level control and the returns via the “blue” cor

12、e of the same cable to the main PCB to be fed to the power amplifier stage. Power Amplifier RadioFans.CN 收音机爱 好者资料库 The power amplifier consists of a fairly conventional Class A driver stage driving a Class AB MOS-FET output stage with Class H supply rail modulation. Each stage will be dealt with in

13、dividually. Class A Driver The input signal returned from the level control is fed via DC blocking capacitor C53A and R59A. DC bias current for the Class A input stage is supplied via R60A, whilst 330pF capacitor C54A prevents any extreme high frequency input signals from reaching the power amplifie

14、r and also provides a low source impedance at high frequencies to ensure frequency stability. The first stage of the Class A driver consists of TR52A and TR53A configured as a long tailed pair differential amplifier. Emitter resistors R62A and R63A de-sensitise the performance of the input stage to

15、parametric variations of the two input transistors. The quiescent current for the input stage is delivered by current source TR51A. Diodes D11A and D12A provide a reference voltage of approximately 1.3V which is applied to the base of TR51A. Approximately half of this (0.65V) will then appear across

16、 R61A (330R) which then sets the current sourced from TR51A collector at approximately 2mA. In the quiescent state half of this current is driven through TR52A and TR53A. Hence the voltage dropped across emitter resistors R62A and R63A will be approximately equal at 100mV. The collector currents of

17、TR52A and TR53A are fed via R67A and R68A to R69A and R70A respectively. Hence, in the quiescent state, R69A and R70A should each exhibit a voltage drop of 2.7V or so. Overall voltage feedback of the amplifier is derived through R64A and R66A. R65A and C55A connected in parallel with R64A provide ph

18、ase lead compensation to maintain good amplifier frequency stability, and a fault in either of these components may result in RF signals being present at the output, or in unusually high distortion. C56A connected in series with R66A gives 100% DC feedback to minimise any DC offset at the output. Th

19、e resultant feedback signal is applied to the base of TR53A. Under normal conditions the signals at the bases of TR52A and TR53A will be identical. However, under fault conditions, such as a DC offset at the output, the base voltages will become offset also. For example, in the event of a large DC o

20、ffset of +50V at the output a positive DC voltage will appear at the feedback point and hence at the base of TR53A. Although this would, in theory, be the full +50V, owing to C56A being rated at only 25V, the voltage will, in practice, be somewhat lower. However, the important issue is that the volt

21、age is positive. In the event the voltage is negative this indicates that the feedback network is faulty (most likely R64A itself). The voltage at TR53A base being positive whilst the base of TR52A is close to 0V will then reverse bias TR53A base-emitter hence turning off the transistor. Hence, no v

22、oltage should appear across R63A and R70A whilst double the normal voltage will appear across R62A and R69A (200mV and 5.4V respectively). Should this not be the case, it indicates a fault in the input stage itself. The output of the input long-tailed-pair (i.e. the voltages across R69A and R70A) ar

23、e fed to a second long-tailed-pair TR56A and TR57A. The bias current for this stage is set by current source TR58A. The base current for TR58A is fed through R72A. TR59A senses the voltage across the emitter resistor of TR58A R77A and “robs” TR58A of base current to maintain approximately 650mV acro

24、ss R77A. Hence the collector current of TR58A is set at approximately 4.3mA which is shared equally between TR56A and TR57A. C58A and C62A provide Miller Feedback around TR56A and TR57A respectively. These capacitors set the dominant pole of the amplifier frequency response, and are therefore critic

25、al for amplifier stability. It should also be noted that either of these capacitors becoming “leaky” (difficult to measure in circuit) will result in a DC offset at the output. The collector of TR57A drives the positive output more-or-less directly (more detail later) whilst the collector of TR56A d

26、rives current mirror TR54A/TR55A via R76A. In the quiescent state R76A will show a voltage drop of around 22V, and the current mirror emitter resistors R74A R73A and will show equal voltage drops of 320mV. Hence, for the same +50V DC offset, described earlier, one would expect no voltage drop across

27、 any of R76A, R73A or R74A, indicating that the feedback is attempting to correct the fault. Likewise, for a negative DC offset one would expect these voltages to be twice their usual value. If this is not the case then the second stage (TR54A-TR59A) is at fault. The loads for TR57A and TR55A are fo

28、rmed by Bootstrapped current sources TR60A/TR61A and TR63A/TR64A respectively. Operation of the two current sources is, in principal, identical so the upper current source TR60A/TR61A only will de described. The load current is sourced from the collector of TR61A, its base being biased through R80A.

29、 The voltage across emitter resistor R79A is sensed by TR60A which then “robs” TR61A of base current to maintain a voltage drop across R79A of approximately 650mV. This sets the collector current of TR61A at approximately 4.3mA. The current source is connected to the +HT rail via R78A. The current t

30、hrough R78A is the sum of TR61A collector current (4.3mA) and the current through R80A (5mA) and, therefore, 43V will be developed across R80A. Capacitors C63A and RadioFans.CN 收音机爱 好者资料库 C64A Bootstrap the current source end of R78A to the output. Therefore, with signal applied, the voltage at this

31、 point will be approximately 100V DC with the output signal superimposed upon it. The outputs of the two current sources TR61A and TR63A are fed through D13A and D14A to vbe multiplier circuit TR62A, which sets the output stage bias. The bias voltage is defined by R81A, R82A and VR1A which is factor

32、y preset for the correct bias setting of 350mV measured between the emitters of TR65A and TR66A. Diode/Zener clamps D15A-D18A limit the maximum gate to source voltage applied to the output stage thereby setting a current limit for protection of the output stage. Units fitted with P1042 re-entrant pr

33、otection daughter boards connect transistors TR1 and TR2 across D16A and D17A respectively. The turn-on of these two transistors is controlled so as to reduce the allowed Gate to Source voltage as the Drain to Source voltage increases, thereby providing closer protection of the output stage. Emitter

34、 followers TR65A and TR66A buffer the Class A driver stage in order to provide more current to drive the output stage. Although the MOS-FET output stage has very high input resistance, requiring little current, the parasitic capacitances will impair its performance without the addition drive current

35、 available. Output Stage The output stage consists of four tiers of seven output devices connected in parallel. TR8A-TR14A form the negative half of the Class AB output stage, whilst TR15A to TR21A form the positive half. Each device has a gate “stopper” resistor R8A- R21A and a Gate to Drain Miller

36、 capacitor C8A-C21A which prevent parasitic oscillation of the output stage. The supply for the output stage is fed from the +LT rails (approximately 70V) via D6A and D7A for the positive and negative halves respectively. In addition, the upper tiers of devices TR1A-TR7A and TR22A-TR28A modulate the

37、 supply to a voltage approximately 20V greater than the output voltage when the output approaches or exceeds the 70V LT supply. There are two important advantages to this system. Firstly, in the “Off” state the output stage is fed from a 70V supply, which reduces the breakdown voltage requirements f

38、or the output stage. Secondly, as the power dissipation in a Class AB output stage is proportional to the square of the supply voltage, for small (-6dB or lower) output signals, the power dissipation is a quarter of what it would be with a conventional design. The upper tiers of the output stage are

39、 driven from TR29A-TR32A, TR37A and TR38A for the positive side, and from TR33A-TR36A, TR39A and TR40A for the negative side. The operation of each half is, in principal, identical so the positive driver only will be described. The Class H driver consists of two current sources TR29A/TR30A and TR31A

40、/TR32A. TR29A/TR30A operate from the +HT supply and are set to source approximately 2mA. TR31A /TR32A operate from the output signal and are set at 4.3mA. When operating correctly, 650mV will be developed across each of R32A and R33A. Zener diode ZD2A is connected between the two current sources and

41、 will normally show a voltage drop of 20V. Zener diode ZD1A is connected between the Cathode of ZD2A and the output of the upper tier of output devices. Hence, in the quiescent state, the Cathode voltage, with respect to 0V, of ZD1A will be approximately +70V, and the Anode to Cathode voltage will b

42、e approximately 650mV. As the two current sources are unbalanced, the lower source will obtain 2mA of its 4.3mA from the upper current source and the remaining 2.3mA of current through ZD1A, thereby biasing the upper tier of the output stage into the off state. As the output voltage increases, less

43、voltage will be dropped across TR32A as it maintains its 4.3mA of collector current. When the output voltage reaches approximately 20V below the +LT rail TR32A will become saturated and the voltage at the Cathode of ZD2A will begin to increase, biasing the upper tier of output devices into the on st

44、ate. Transistors TR37A and TR38A are configured as emitter followers to increase the drive current available to the output stage. Hence the gate drive applied to the upper tier of devices will follow the output with an additional 20V of DC offset. Faults in the Output Stage Output device failure is

45、usually in one of three modes. A)Device short Drain to Source B)Device short Gate to Source C) Device open Drain to Source Failure mode A) is usually exhibited as a DC offset at the output (or if the device is in the upper tier of devices as the modulated rail being “stuck” at the full +140V). Such

46、a fault will be revealed as a Drain to Source short circuit across the offending tier of devices. To identify which device(s) is faulty measure the resistance between Gate and Source of each device in the faulty tier with the multi-meter set to its 2kOhm range. A faulty device will show as a resista

47、nce measurement of less than 1k1 (usually 0-100 Ohms). Failure modes B) and C) will be exhibited as premature clipping on one half-cycle of the output. This fault will not, however, be shown with the amplifier unloaded. In the event the fault persists with no load connected, the fault is likely to b

48、e elsewhere. Devices suffering from failure mode B) can be easily identified with the simple multi-meter test outlined above. Failure mode C) is a little more difficult to identify. The simplest method is to connect a “wander” lead to the Source connection of the offending tier of devices. Touch eac

49、h gate lead of that tier of devices with the “wander” lead in turn observing the output waveform. Each time a device is shorted Gate to Source the clipping will become more pronounced. A faulty device will be revealed by less dramatic additional clipping. Multimeter Testing of Output Devices Once a device has been removed from circuit it is comparatively simple to check whether it is operating correctly. The following routine is for an N-Channel (K1058) device. The routine for testing a P-Channel device is identical with Red and Black leads swapped. Set the Multi-Meter to its 200 Ohm range.