Denon-S102-hts-sm维修电路原理图.pdf

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1、TOKYO, JAPAN Denon Brand Company, D (5V tolerant input). TDMDX 25 OTDM transmit data output. RSELILCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-k? resistor; read only during reset. TDMDR28ITDM receive data input; (5V tolerant input). TDMCLK29ITDM clock input; (5V tolerant input)

2、. TDMFS30ITDM frame sync input; (5V tolerant input). TDMTSC#31OTDM output enable. TWS 32 OAudio transmit frame sync output. SEL_PLL2ISystem and DSCK output clock frequency selection is made at the rising edge of RESET#. The matrix below lists the available clock frequencies and their respective PLL

3、bit settings. Strapped to VCC or ground via 4.7-k? resistor; read only during reset. RSELSelection 016-bit ROM 18-bit ROM SEL_PLL2SEL_PLL1SEL_PLL0PLL Settings 000DCLK ? ?.5 001DCLK ? 5.0 010Bypass 011DCLK ? 4.0 100DCLK ? 4.25 101DCLK ? 4.75 110DCLK ? 5.5 111DCLK ? 6.0 47 S-102 TSD0 33 OAudio transmi

4、t serial data output 0. SEL_PLL0IRefer to the description and matrix for SEL_PLL2 pin 32. TSD1 36 OAudio transmit serial data output 1. SEL_PLL1IRefer to the description and matrix for SEL_PLL2 pin 32. TSD237OAudio transmit serial data output 2. This pin must be pulled down to VSS via a 4.7-k? resis

5、tor for proper operation. TSD338OAudio transmit serial data output 3. MCLK39I/OAudio master clock for audio DAC. TBCK40I/OAudio transmit bit clock. TBCK is an input during reset and subsequently is programmed as an output via the AUDIOXMT register (addr 0 x2000D00Ch, bit 4). SEL_PLL3 41 IClock sourc

6、e select. Strapped to VCC or ground via 4.7-k? resistor; read only during reset. SPDIF_OUTOS/PDIF output. SPDIF_IN42IS/PDIF input; (5V tolerant input). RSD45IAudio receive serial data; (5V tolerant input). RWS46IAudio receive frame sync; (5V tolerant input). RBCK47IAudio receive bit clock; (5V toler

7、ant input). CAMIN3 48 ICamera YUV 3. PIXIN3ICCIR656 input pixel 3. XIN49I27-MHz crystal input. XOUT50O27-MHz crystal output. AVEE51PAnalog power for PLL. AVSS52GAnalog ground for PLL. DMA11:053-58, 61-66ODRAM address bus. DCAS#69ODRAM column address strobe. DOE# 70 ODRAM output enable. DSCK_ENODRAM

8、clock enable. DWE#71ODRAM write enable. DRAS#72ODRAM row address strobe. DMBS073ODRAM bank select 0. DMBS174ODRAM bank select 1. DB15:077-82, 85-90, 93-96I/ODRAM data bus. DCS1:0#97,100ODRAM chip select. DQM101OData input/output mask. DSCK102OOutput clock to DRAM. NamePin NumbersI/ODefinition SEL_PL

9、L3Clock Source 0Crystal oscillator 1DCLK input 48 S-102 DCLK105IClock input to PLL; (5V tolerant input). UDAC 106 OVideo DAC output. F: CVBS/chroma signal for simultaneous mode. Y: Luma component for YUV and Y/C processing. C: Chrominance signal for Y/C processing. U: Chrominance component signal fo

10、r YUV mode. V: Chrominance component signal for YUV mode. YUV0OYUV pixel 0 output data. PIXOUT0OCCIR656 output pixel 0. VREF 107 IInternal voltage reference to video DAC. Bypass to ground with 0.1-?F capacitor. YUV1OYUV pixel 1 output data. PIXOUT1OCCIR656 output pixel 1. CDAC 108 OVideo DAC output.

11、 Refer to description and matrix for UDAC pin 106. YUV2OYUV pixel 2 output data. PIXOUT2OCCIR656 output pixel 2. COMP 109 ICompensation input. Bypass to ADVEE with 0.1-?F capacitor. YUV3OYUV pixel 3 output data. PIXOUT3OCCIR656 output pixel 3. RSET 110 IDAC current adjustment resistor input. YUV4OYU

12、V pixel 4 output data. PIXOUT4OCCIR656 output pixel 4. NamePin NumbersI/ODefinition Value F DAC (pin 115) V DAC (pin 114) Y DAC (pin 113) C DAC (pin 108) U DAC (pin 106) 0CVBS/ChromaCVBS1YCN/A 1CVBS/ChromaCVBS1YCCVBS2 2CVBS/ChromaN/AYCN/A 3CVBS/ChromaCVBS1N/AN/ACVBS2 4CVBS/ChromaCVBS1N/AN/AN/A 5CVBS

13、/ChromaCVBS1YPbPr 6CVBS/ChromaN/AYPbPr 7N/ASYNCGBR 8CVBS/ChromaChromaYPbPr 9CVBSCVBS1GBR 10CVBSCVBS1GRB 11N/ASYNCGRB 12CVBS/ChromaN/AYPrPb 13CVBS/ChromaCVBS1YPrPb 14ChromaYGRB 49 S-102 ADVEE111PAnalog power for video DAC. ADVSS112GAnalog ground for video DAC. YDAC 113 OVideo DAC output. Refer to des

14、cription and matrix for UDAC pin 106. YUV5OYUV pixel 5 output data PIXOUT5OCCIR656 output pixel 5. VDAC 114 OVideo DAC output. Refer to description and matrix for UDAC pin 106. YUV6OYUV pixel 6 output data. PIXOUT6OCCIR656 output pixel 6. FDAC 115 OVideo DAC output. Refer to description and matrix f

15、or UDAC pin 106. YUV7OYUV pixel 7 output data. PIXOUT7OCCIR656 output pixel 7. PCLK2XSCN 116 I/O27-MHz video output pixel clock. CAMIN4ICamera YUV 4. PIXIN4ICCIR656 input pixel 4. PCLKQSCN 117 O13.5-MHz video output pixel clock. AUX32I/OAux3 data I/O; (5V tolerant input). CAMIN5ICamera YUV 5. PIXIN5

16、ICCIR656 input pixel 5. VSYNC# 118 I/OVertical sync; (5V tolerant input). AUX31I/OAux3 data I/O; (5V tolerant input). CAMIN6ICamera YUV 6. PIXIN6ICCIR656 input pixel 6. HSYNC# 119 I/OHorizontal sync; (5V tolerant input). AUX30I/OAux3 data I/O; (5V tolerant input). CAMIN7ICamera YUV 7. PIXIN7ICCIR656

17、 input pixel 7. HD5:0 122-127 I/OHost data bus lines; (5V tolerant input). DCI5:0I/ODVD channel data I/O; (5V tolerant input). AUX15:0I/OAux1 data I/O; (5V tolerant input). HD6 128 I/OHost data bus line; (5V tolerant input). DCI6I/ODVD channel data I/O; (5V tolerant input). AUX16I/OAux1 data I/O; (5

18、V tolerant input). VFD_DOUTIVFD data output. HD7 131 I/OHost data bus line; (5V tolerant input). DCI7I/ODVD channel data I/O; (5V tolerant input). AUX17I/OAux1 data I/O; (5V tolerant input). VFD_DINIVFD data input. NamePin NumbersI/ODefinition 50 S-102 HD8 132 I/OHost data bus line; (5V tolerant inp

19、ut). DCI_FDS#I/ODVD input sector start; (5V tolerant input). AUX20I/OAux2 data I/O; (5V tolerant input). VFD_CLKIVFD clock input. HD9 133 I/OHost data bus line; (5V tolerant input). AUX21I/OAux2 data I/O; (5V tolerant input). HD10 134 I/OHost data bus line; (5V tolerant input). AUX22I/OAux2 data I/O

20、; (5V tolerant input). HD11 135 I/OHost data bus line; (5V tolerant input). AUX23I/OAux2 data I/O; (5V tolerant input). IRQOIRQ. HD12 136 I/OHost data bus line; (5V tolerant input). AUX24I/OAux2 data I/O; (5V tolerant input). C2POIC2PO error correction flag from CD-ROM; (5V tolerant input). HD13 137

21、 I/OHost data bus line; (5V tolerant input). AUX25I/OAux2 data I/O; (5V tolerant input). SPI16550 UART serial port input. HD14 140 I/OHost data bus line; (5V tolerant input). AUX26I/OAux2 data I/O; (5V tolerant input). HD15 141 I/OHost data bus line; (5V tolerant input). AUX27I/OAux2 data I/O; (5V t

22、olerant input). IRIIR remote control input; (5V tolerant input). HWRQ# 142 OHost write request. DCI_REQ#ODVD control interface request. AUX41I/OAux4 data I/O; (5V tolerant input). HRRQ# 143 OHost read request. AUX40I/OAux4 data I/O; (5V tolerant input). CAMIN2ICamera YUV 2. PIXIN2ICCIR656 input pixe

23、l 2. HIRQ 144 I/OHost interrupt. DCI_ERR#I/ODVD channel data error; (5V tolerant input). AUX47I/OAux4 data I/O; (5V tolerant input). HRST# 145 OHost reset. AUX35I/OAux3 data I/O; (5V tolerant input). HIORDY 146 IHost I/O ready. AUX33I/OAux3 data I/O; (5V tolerant input). NamePin NumbersI/ODefinition

24、 51 S-102 HWR# 149 I/OHost write. DCI_CLKI/ODVD channel data clock; (5V tolerant input). AUX45I/OAux4 data I/O; (5V tolerant input). HRD# 150 OHost read. DCI_ACK#I/ODVD channel data valid; (5V tolerant input). AUX46I/OAux4 data I/O; (5V tolerant input). HIOCS16# 151 IDevice 16-bit data transfer. AUX

25、34I/OAux3 data I/O; (5V tolerant input). CAMCLKICamera port pixel clock input. PIXIN_CLKICCIR656 input pixel clock. HCS1FX# 152 OHost select 1. AUX37I/OAux3 data I/O; (5V tolerant input). HCS3FX# 153 OHost select 3. AUX36I/OAux3 data I/O; (5V tolerant input). HA2:0 154, 155, 158 I/OHost address bus.

26、 AUX44:2I/OAux4 data I/Os; (5V tolerant input). AUX0 160 I/OAuxiliary port 0 (open collector); (5V tolerant input). I2CDATAI/OI2C data I/O; (5V tolerant input). AUX1 161 I/OAuxiliary port 1 (open collector); (5V tolerant input). I2C_CLKI/OI2C clock I/O; (5V tolerant input). AUX2 162 I/OAuxiliary por

27、t; (5V tolerant input). IOW#OI/O write strobe (LCS1). AUX3 165 I/OAuxiliary port; (5V tolerant input). IOR#OI/O read strobe (LCS1). AUX4-7166-169I/OAuxiliary ports; (5V tolerant input). LOE#170ORISC port output enable. LCS0# 173 ORISC port chip select 0. PIXOUT_CLKOCCIR656 output pixel clock. LCS3:1

28、#174-176ORISC port chip select 3:1. LD15:0 178-182, 185-191, 194-197 I/ORISC port data bus; (5V tolerant input). LWRLL#198ORISC port low-byte write enable. LWRHL#199ORISC port high-byte write enable. CAMIN0 202 ICamera YUV 0. PIXIN0ICCIR656 input pixel 0. CAMIN1 203 ICamera YUV 1. PIXIN1ICCIR656 inp

29、ut pixel 1. NamePin NumbersI/ODefinition 52 S-102 DSP21367 (IC401: 1U-3836) 53 S-102 M30627FHPGP (IC301: 1U-3836) Pin No Port Function Port setting Port NameExplanation 1VREF-VREFReference Voltage Input for A/D converter 2AVCC-AVCCPositive power 3P97/SIN4IDSP_MISOSerial Data input from DSP 4P96/SOUT

30、4ODSP_MOSISerial Data output to DSP 5P95/CLK4ODSP_CKSerial Clock output to DSP 6P94ODSP_PWRDSP Power ON/OFF output 7P93OFL_CSChip Enable output to FLD 8P92/SOUT3OFL_DOUTSerial Data output to FLD 9P91/SIN3O/FL_RSTReset output to FLD 10P90/CLK3OFL_CLKSerial Clock output to FLD 11P141O/VMONI_SELBSelect

31、 signal output of VIDEO OUTPUT(L:AUX1/2,H:DVD). 12P140O/FLI_RSTReset output to FLI2310 13BYTE-BYTEGND 14CNVCS-CNVSSSelect input of Flash Memory write Mode 15P87OON/_STBYMain POWER ON/STANDBY switching output. H:ON 16P86O/VMONI_SELASelect signal output of VIDEO OUTPUT (H:AUX1, L:AUX2) 17RESETIRSTRese

32、t input 18XOUTOX1Xtal output 19VSS-VSSGND 20XINIX2Xtal input 21VCC1-VCC1Positive power 22P85/NMII/NMIPositive power 23P84/INT2I/DIR_INTInterrupt input from DIR 24P83/INT1INT/BE_AUDIO_RSTAudio Reset input from ESS 25P82/INT0INTBE CSCS Interrupt input from ESS 54 S-102 26P81ECP_DOWN( 50/60Hz )50Hz/60H

33、z AC input 27P80IPWB_CHKChecking PWB input 28P77O/SMONI_SELBSelecteYC Video outputB 29P76O/SMONI_SELASelecte YC Video outputA 30P75IVOL_BVOL encoder Pulse-B input 31P74IVOL_AVOL encoder Pulse-A input 32P73/CTS2ONC(L:Output)Not Used:N.C. 33P72/CLK2I/TEMP_DETTemperature Detect signal input from posist

34、er 34P71/RXD2IIPOD_D_MRXDSerial Data input from IPOD 35P70/TXD2OIPOD_D_MTXDSerial Data output to IPOD 36P67/TXD1OF_TXD2Serial Data out to Flash Memory. 37VCC1-VCC1Positive power 38P66OF_RXD2Serial Data input from Flash Memory. 39VSS-VSSGND 40P65OLED_ORGOrenge(Yellow)LED output. L:ON 41P64ODC/DC_ONPo

35、wer ON/OFF output to DC/DC Converter. H: Power ON 42TXD0SOBE_STXDSerial Data output to ESS 43RXD0SIBE_SRXDSerial Data input from ESS 44CLK0SIBE_CLKSerial Clock input from ESS 45P60/CTS0ONC(L:Output)Not Used:N.C. 46P137ONC(L:Output)Not Used:N.C. 47P136OHD/_SDSelect signal output of Video Encoder Cloc

36、k ( L:SD, H:HD) 48P135O/CHOP_ONCHOPER REG. ON/OFF output. L:ON 49P134OHDMI_DEBG6For HDMI Debug 50P57O/ENC_RSTVideo Encoder Reset output 51P56ONC(L:Output)Not Used:N.C. 52P55/EPMOF_EPM2Writing Port for Flash Memory. 53P54IAUX_SWFront AUX IN insert detect signal input. H: Detected 54P133IHP_SWHEAD PHO

37、NE insert detect signal input. H: Detected 55P132ONC(L:Output)Not Used:N.C. 56P131OHDMI_OEHDMI Output Enable(Active Low) 57P130O/VPLD_RSTReset output to VPLD. 58P53ONC(L:Output)Not Used:N.C. 59P52OLED_REDRed LED output. L:ON 60P51OLED_BLUBlue LED output. H:ON 61P50/CEO/F_CE2Chip Enable output to Fla

38、sh Memory. 62P127ONC(L:Output)Not Used:N.C. 63P126OE2P_CSChip Select output to EEPROM 64P125OSAN_CEChip Enable output to TUNER/RDS IC 65P47OE2P_CLK Serial Clock output to EEPROM 66P46OE2P_MOSISerial Data output to EEPROM 67P45OFNVL_DASerial Data output to FUNC/VOL IC. 68P44OFNVL_CKSerial Clock outpu

39、t to FUNC/VOL IC. 69P43OFNVL_CEChip Enable output to FUNC/VOL IC. 70P42IE2P_MISOSerial Data input to EEPROM 71P41ISAN_MISOSerial Data input from TUNER/RDS IC 72P40ITU_STEREOSTEREO indicator input from FM/AM TUNER pack 73P37ITUNEDTUNED detect input from FM/AM TUNER pack 74P36O/TU_MUMUTE output to TUN

40、ER. L:MUTE 75P35OTU_POWERTUNER Power ON/OFF output. H: Power ON 76P34O/SAN_RSTReset output to TUNER/RDS IC 77P33OSP_RLSP RELAY ON/OFF output. H:ON 78P32ICODEC_MISOSerial Data input from CODEC 79P31ONC(L:Output)Not Used:N.C. 80P124OSAN_CK Serial Clock output to TUNER/RDS IC Pin No Port Function Port

41、setting Port NameExplanation 55 S-102 :Reserved 81P123OSAN_MOSISerial Data output to TUNER/RDS IC 82P122O/CODEC_RSTReset output to CODEC 83P121OPRE_MUTE_SUBMUTE output to PRE OUT. H:MUTE 84P120OHP_MUTE_SUBMUTE output to HEAD PHONE output. H:MUTE 85VCC2-VCC2Positive power 86P30OBE/_DIRSelect audio li

42、ne output.(H:ESS,L:DIR) 87VSS-VSSGND 88P27OCODEC_CEChip Enable output to CODEC 89P26ONC(L:Output)Not Used:N.C. 90P25ODSP_IO_MUTEDSP IO MUTE output(H:Mute) 91P24O/AD/DIGSelect audio line output.(H:DIGITAL, L:ADC IN) 92P23O/ERR_MUTEMUTE output at DSP Error. 93P22O/BSEBit Stream Enable output(L:Enable)

43、 94P21ONC(L:Output)Not Used:N.C. 95P20ONC(L:Output)Not Used:N.C. 96INT5INT/PROTECTProtect Signal input. 97P16ONC(L:Output)Not Used:N.C. 98INT3INT/REMOCONRemote Control signal input 99P14ONC(L:Output)Not Used:N.C. 100P13OPRE_MUTE_MAINMUTE output to Output(H:Mute). 101P12O/COMP_MUTECOMPONENT VIDEO Mut

44、e output(H:Mute) 102P11O/S/V_MUTES/COMPOSITE VIDEO Mute output(H:Mute) 103P10O/BE RSTReset output to ESS 104P07ODRV_ONDRIVE POWER ON output(H:P.ON) 105P06OSYS_REQSYSTEM REQEST output to ESS. 106P05IBE ONActive Flag input from ESS. 107P04ONC(L:Output)Not Used:N.C. 108P03ONC(L:Output)Not Used:N.C. 109

45、P02O/DIR_RSTReset output to DIR. 110P01ODIR_CEChip Enable output to DIR 111P00ODIR/CODEC_CKSerial Clock output to DIR/CODEC. 112P117IDIR_MISOSerial Data input from DIR. 113P116ODIR/CODEC_MOSISerial Data output to DIR/CODEC 114P115O/DSPROM_RSTReset output to DSP ROM. 115P114O/DSP_RSTReset output to D

46、SP. 116P113ODSP_CSChip Select output to DSP 117P112IFLAG0DSP FLAG0 input 118P111OFAN_ONFAN ON/OFF output.H:FAN ON 119P110OFAN SPEEDFAN SPEED Control output(H:Slow L:Fast) 120P107/AN7IPull uPull up 121P106/AN6ADKEY2Unit Operation Button input2 122P105/AN5ADKEY1Unit Operation Button input1 123P104/AN4

47、ADKEY0Unit Operation Button input0 124P103/AN3ADMODE2_S102Initial Setting input for Region No of DVD. 125P102/AN2ADMODE1_S102Initial Setting input the destination.(E2,E3) 126P101/AN1OPull upPull up 127AVSS-AVSSGND 128SW1_INADSW1_INSelect signal input of Video Signal. (H:HDMI/M:PROGRE/L:INTERLACE) Pi

48、n No Port Function Port setting Port NameExplanation 56 S-102 W9864G2GH-7 (IC402: 1U-3836) PIN DESCRIPTION PIN NAMEFUNCTIONDESCRIPTION A0A10AddressMultiplexed pins for row and column address. Row address: A0A10. Column address: A0A7. A10 is sampled during a precharge command to determine if all bank

49、s are to be precharged or bank selected by BS0, BS1. BS0, BS1Bank SelectSelect bank to activate during row address latch time, or bank to read/write during address latch time. DQ0DQ31Data Input/ Output Multiplexed pins for data output and input. CS Chip SelectDisable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. RAS Row Address Strobe Command input. When sampled at the rising edge of the clock RAS, CAS and WE define the operation to be executed. CAS Column Address Strobe Referred to RAS WE Write Enable Ref