Hitachi-DVP345E-cd-sm维修电路原理图.pdf
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1、CAUTION: Before servicing this chassis, it is important that the service technician read the “Safety Precautions” and “Product Safety Notices” in this service manual. ATTENTION: Avant deffectuer lentretien du chassis, le technicien doit lire les Prcautions de scurit et les Notices de scurit du produ
2、it prsents dans le prsent manuel. VORSICHT: Vor ffnen des Gehuses hat der Service-Ingenieur die Sicherheitshinweise“ und Hinweise zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen. SERVICE MANUAL MANUEL DENTRETIEN WARTUNGSHANDBUCH Data contained within this Service manual is subject to alte
3、ration for improvement. Les donnes fournies dans le prsent manuel dentretien peuvent faire lobjet de modifications en vue de perfectionner le produit. Die in diesem Wartungshandbuch enthaltenen Spezifikationen knnen sich zwecks Verbesserungen ndern. SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR
4、 IMPROVEMENT Digital Versatile Disk August 2004 No. 9403 DV-P345UK DV-P345E Downloaded Free from http:/www.free-service- RadioFans.CN 收音机爱 好者资料库 2 1. GENERAL DESCRIPTION 1.1 ZR36768 The ZR36768 Disc Loader Controller and Decoder Device can control disc loaders and read bitstreams using the following
5、 media: DVD-ROM, DVDRW, CD-DA, CD-ROM, CD-R and CD-R/W discs. The device can decode bitstreams and process navigation data of the following formats: DVD-Video, DVD-Audio, CD-DA, VCD (Video-CD), SVCD (Super Video-CD) and MP3. The features of this chip can be listed as follows: Disc loader control and
6、 bitstream processing 8 analog inputs (low frequency) for servo errors and RF signals envelope monitoring 11 actuators drive or control outputs. Two analog outputs through 11 bits DACs (e.g. for the tracking and focus coils), and 9 PWM outputs divided into two type groups: High frequency, “uniform”
7、type PWMs (e.g. for the spindle and sled motor drives), and lower frequency “regular” type PWMs, which can be used e.g. for programmed tray motion or RF amplifier parameter setting. Processing of spindle and sled position read-back devices All servo loop closure, closed loop control and error handli
8、ng. Bitstream extraction using AGC, bit clock frequency detection and phase lock loop, adaptive threshold calculations, Viterbi bit decision, defect detection, frame sync detection and EFM/P conversion. CD sub-code extraction and processing. CD ECC for all CD types. CD EDC for Mode 1 discs DVD ECC a
9、nd EDC. Track buffer and re-try management Decoding Single chip solution for playback of DVD-Video, DVD-Audio Video-CD, Super Video-CD, CD- DA, and MP3 from CD-ROM, CD-R or CD-R/W. Decoding and display of high resolution MPEG 1 and MPEG 2 still image sequences (including ASVs from DVD-Audio but with
10、out the transition effects). Decoding of Dolby AC-3, DTS or MLP multi-channel audio. Decoding of MPEG 1 or MPEG 2 layer II mono, stereo, or multi-channel audio. Decoding of MPEG 1 or MPEG 2 Layer 3 (MP3) mono and stereo audio. PCM and LPCM audio playback from DVD-Video, DVD-Audio, Video-CD and CD-DA
11、. Decoding and playback of sub-picture (including Highlight), and closed captions (“line 21”) data from DVD-Video discs. Interlaced digital and analog video output or progressive analog video output. NTSC and PAL standards. PAL playback of NTSC discs and NTSC playback of PAL discs. Special modes sup
12、port like pause, slow motion, fast forward and reverse. Post Processing Audio down mixing, sample rate conversion, Dolbys pro-logic and 3D enhancement. Karaoke mixing of decoded audio and two channels of input audio. On-chip OSD engine with 32 color (24-bit YUV) palette, up to 8 levels of transparen
13、cy; and capability of blinking regions and vertical scrolling. On-screen and off-screen OSD memory regions for animation support. 1/4 pixel and 1/4 line pan (high, low) - Flash+SRAM (for debug monitor); (low, high) - First debug UART; (low, low) - Flash (low) or Level sampled during RESET MEMAD0 / O
14、 / PNVM/SRAM address bus output / 49 BOOTSEL1 I CPU SW boot (and execute) source selection - Flash (low) or first debug UART (high). Level sampled during RESET 23 MEMWR# O PNVM/SRAM write enable (active low) output. 44 MEMRD# O PNVM/SRAM read enable (active low) output. Downloaded Free from http:/ww
15、w.free-service- 11 47 MEMCS0# O PNVM/SRAM chip select (active low) output MEMCS1# / O / PNVM/SRAM chip select (active low) output/ 2 GPCI/O18 I/O General purpose input/output pin, monitored/controlled by the CPU or DSP SW Power Signals (56 pins) 12,32,50 ,62,72,8 3,91,101 ,107,125 ,151,202 GNDP S Di
16、gital periphery ground of 3.3 V supply (12 pins) 3,21,41, 52,58,68 ,76,87,9 7,105,12 7,144,20 4 VDDP S 3.3 V Digital periphery power supply. (13 pins) 51,154 VDDP-IP S 3.3 V periphery reference voltage (2 pins) 117 GNDP-A2 S Digital ground of filtered 3.3 V supply for AMCLK 119 VDDP-A2 S 3.3 V filte
17、red digital power supply for AMCLK 79 GNDPCLK S Digital ground of filtered 3.3 V supply for PCLK 81 VDDPCLK S 3.3 V filtered digital power supply for PCLK 29,66,95 ,121,190 GNDC S Digital core ground of 1.8 V supply (5 pins) 25,64,93 ,123,192 VDDC S 1.8 V Digital core power supply. (5 pins) 138 GNDA
18、 S Ground plane of internal PLL circuit 140 VDDA S 1.8 V Power supply for internal PLL circuit 160 VDDDAC S 3.3 V Analog power supply for the video DACs 164 GNDDACP / S Grounds for the video DACs 3.3 V analog power supply (2 pins) 157 GNDDACD 165 GNDDABS2 S Common Ground for the video and SERVO DACs
19、 166 GNDDACPS / S Grounds for the SERVO DAC 3.3 V analog power supply (2 pins) 170 GNDDACDS 174 GNDAFERF S Analog RF (AFE) ground of 3.3 V supply 171 VDDAFERF S 3.3 V Analog RF (AFE) power supply 186 GNDAFES S Analog SERVO (AFE) ground of 3.3 V supply 175 VDDAFES S 3.3 V Analog SERVO (AFE) power sup
20、ply 168 VDDDACS S 3.3 V SERVO DACs power supply 195 GNDPWMS S SERVO PWMs ground of 3.3 V supply 197 VDDPWMS S 3.3 V SERVO PWM power supply Downloaded Free from http:/www.free-service- 12 2.1 SYSTEM BLOCK DIAGRAM A sample system block diagram for the MT1379 DVD player board design is shown in the fol
21、lowing figure: 3. AUDIO OUTPUT The ZR36768 supports two-channel to eight-channel analog audio output. This version has two- channel output. The ZR36768 also provides digital output in S/PDIF format. The board supports both optical and coaxial SPDIF outputs. 4. AUDIO DACS The ZR36768 supports several
22、 variations of an I2S type bus. The I2S format uses four stereo data lines and three clock lines. The I2S data and clock lines can be connected directly to one or more audio DAC to generate analog audio output. The two-channel DAC is a Cirrus Logic CS4392. The DACs support up to 192kHz sampling rate
23、. The outputs of the DACs are differential, not single ended so a buffering circuit is required. The buffer circuit use a National LM833 op-amp to perform the low-pass filtering and the buffering. 5 .VPU - VIDEO PROCESSING UNIT The VPU is responsible for all video output processing and timing. It ou
24、tputs 8 bit (CCIR 656 type) digital interlaced video and separate syncs. It can also output interlaced composite, S- or component analog video, or progressive components analog video. The VPU units have two operating modes: Interlaced when the output is interlaced and Progressive when the output is
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