Onkyo-DT9904S-cd-sm维修电路原理图.pdf
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1、SERVICE MANUAL DT9904S RadioFans.CN 收音机爱 好者资料库 CONTENTS 1. SAFETY PRECAUTIONS1 2. PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO ELECTROSTATICALLY SENSITIVE(ES)DEVICES1 4. PREVERTION OF STATIC ELECTRICITY DISCHARGE3 5. ASSEMBLING AND DISASSEMBLING THE MECHANISM UNIT4 5.1 OPTICAL PICKUP UNIT EXPLOSED
2、VIEW AND PART LIST 4 5.2 BRACKET EXPLOSED VIEW AND PART LIST 6 6. ELECTRICAL CONFIRMATION8 6.1 VIDEO OUTPUT (LUMINANCE SIGNAL) CONFIRMATION8 6.2 VIDEO OUTPUT(CHROMINANCE SIGNAL) CONFIRMATION9 7. MPEG BOARD CHECK WAVEFORM10 8. AM29LV160D11 9. SCHEMATIC 2, 3 Clocks 8.1 HY57V641620HG 16 HY57V641620HG P
3、IN CONFIGURATION PIN DESCRIPTION PINPIN NAMEDESCRIPTION CLKClock The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK CKEClock Enable Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self r
4、efresh CSChip SelectEnables or disables all inputs except CLK, CKE and DQM BA0,BA1 Bank Address Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 A11Address Row Address : RA0 RA11, Column Address : CA0 CA7 Auto-precharge flag : A10 RAS, CAS, WE R
5、ow Address Strobe, Column Address Strobe, Write Enable RAS, CAS and WE define the operation Refer function truth table for details LDQM, UDQMData Input/Output MaskControls output buffers in read mode and masks input data in write mode DQ0 DQ15Data Input/OutputMultiplexed data input / output pin VDD/
6、VSSPower Supply/GroundPower supply for internal circuits and input buffers VDDQ/VSSQData Output Power/GroundPower supply for output buffers NCNo ConnectionNo connection VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS 1 2 3 4 5 6 7 8 9 10
7、 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 54pin TSOP II 400mil x 875mil 0.8mm pin pitch 17 HY57
8、V641620HG FUNCTIONAL BLOCK DIAGRAM 1Mbit x 4banks x 16 I/O Synchronous DRAM X decoders State Machine A0 A1 A11 BA0 BA1 Address buffers Address Registers Mode Registers Row Pre Decoders Column Pre Decoders Column Add Counter Row active Column Active Burst Counter Data Out Control CAS Latency Internal
9、 Row counter DQ0 DQ1 DQ14 DQ15 refresh Self refresh logic for VDD-VEElevel differences above 13V, a VDD-VSS of at least 4.5V is required). For example, if VDD = +4.5V, VSS = 0V, and VEE= -13.5V, analog signals from -13.5V to +4.5V can be controlled by digital inputs of 0V to 5V. These multiplexer ci
10、rcuits dissipate extremely low quiescent power over the full VDD-VSS and VDD-VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic “1” is present at the inhibit input terminal, all channels are off. The CD4051B is a single 8-Channel multiplexer having three b
11、inary control inputs, A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to the output. The CD4052B is a differential 4-Channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary
12、 input signals select 1 of 4 pairs of channels to be turned on and connect the analog inputs to the outputs. The CD4053B is a triple 2-Channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are c
13、onnected in a single-pole, double-throw confi guration. When these devices are used as demultiplexers, the “CHANNEL IN/OUT” terminals are the outputs and the “COMMON OUT/IN” terminals are the inputs. Features Wide Range of Digital and Analog Signal Levels - Digital . . . . . . . . . . . . . . . . .
14、. . . . . . . . . . . . . 3V to 20V - Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20VP-P Low ON Resistance, 125 (Typ) Over 15VP-PSignal Input Range for VDD-VEE = 18V High OFF Resistance, Channel Leakage of 100pA (Typ) at VDD-VEE = 18V Logic-Level Conversion for Digital Addres
15、sing Signals of 3V to 20V (VDD-VSS = 3V to 20V) to Switch Analog Signals to 20VP-P (VDD-VEE = 20V) Matched Switch Characteristics, rON = 5 (Typ) for VDD-VEE = 15V Very Low Quiescent Power Dissipation Under All Digital- Control Input and Supply Conditions, 0.2W (Typ) at VDD-VSS = VDD-VEE = 10V Binary
16、 Address Decoding on Chip 5V, 10V and 15V Parametric Ratings 10% Tested for Quiescent Current at 20V Maximum Input Current of 1A at 18V Over Full Package Temperature Range, 100nA at 18V and 25oC Break-Before-Make Switching Eliminates Channel Overlap Applications Analog and Digital Multiplexing and D
17、emultiplexing A/D and D/A Conversion Signal Gating Ordering Information PART NUMBER TEMP.RANGE (oC)PACKAGE CD4051BF, CD4052BF, CD4053BF -55 to 12516 Ld CERAMIC DIP CD4051BE, CD4052BE, CD4053BE -55 to 12516 Ld PDIP CD4051BM, CD4051BNS-55 to 12516 Ld SOIC CD4051BPW, CD4052BPW, CD4053BPW -55 to 12516 L
18、d TSSOP August 1998 - Revised March 2000 /Title (CD405 1B, CD4052 B, CD4053 B) /Sub- ject (CMOS Analog Multi- plex- ers/Dem ultiplex- ers with Logic Level Conver- sion) /Author () /Key- words (Harris Semi- conduc- tor, CD4000 8.3 CD4052B 22 Pinouts CD4051B (PDIP, CDIP, SOIC, TSSOP) TOP VIEW CD4052B
19、(PDIP, CDIP, TSSOP) TOP VIEW CD4053B (PDIP, CDIP, TSSOP) TOP VIEW 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 4 6 COM OUT/IN 7 5 INH VSS VEE VDD 1 0 3 A B C 2 CHANNELS IN/OUT CHANNELS IN/OUT CHANNELS IN/OUT 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 0 2 COMMON “Y” OUT/IN 3 1 INH VSS VEE VDD 1 COMMON “X” OUT/
20、IN 0 3 A B 2 Y CHANNELS IN/OUT Y CHANNELS IN/OUT X CHANNELS IN/OUT X CHANNELS IN/OUT 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 by bx cy OUT/IN CX OR CY IN/OUT CX INH VSS VEE VDD OUT/IN ax OR ay ay ax A B C OUT/IN bx OR by IN/OUT IN/OUT Functional Block Diagrams CD4051B 11 10 9 6 A B C INH 134251121514
21、TG TG TG TG TG TG TG TG 3 COMMON OUT/IN 01234567 BINARY TO 1 OF 8 DECODER WITH INHIBIT LOGIC LEVEL CONVERSION 87VSSVEE 16 V DD CHANNEL IN/OUT All inputs are protected by standard CMOS protection network. CD4051B, CD4052B, CD4053B 23 CD4052B CD4053B Functional Block Diagrams (Continued) 12111514 0123
22、 3210 X CHANNELS IN/OUT Y CHANNELS IN/OUT BINARY TO 1 OF 4 DECODER WITH INHIBIT 13 3 COMMON Y OUT/IN COMMON X OUT/IN 78 16 6 9 10 A B INH VSSVEE VDD TG TG TG TG TG TG TG TG 4251 LOGIC LEVEL CONVERSION 11 10 9 6 A B C INH 12351213 TG TG TG TG TG TG 4 COMMON OUT/IN axaybxbycxcy 8 7VSSVEE 16 V DD IN/OU
23、T 15 14 BINARY TO 1 OF 2 DECODERS WITH INHIBIT LOGIC LEVEL CONVERSION VDD All inputs are protected by standard CMOS protection network. COMMON OUT/IN COMMON OUT/IN ax OR ay bx OR by cx OR cy CD4051B, CD4052B, CD4053B 24 TRUTH TABLES INPUT STATES “ON” CHANNEL(S)INHIBITCBA CD4051B 00000 00011 00102 00
24、113 01004 01015 01106 01117 1XXXNone CD4052B INHIBITBA 0000 x, 0y 0011x, 1y 0102x, 2y 0113x, 3y 1XXNone CD4053B INHIBITA OR B OR C 00ax or bx or cx 01ay or by or cy 1XNone X = Dont Care CD4051B, CD4052B, CD4053B 25 123 1234 56 A B C D E A B C D E F 1 2 3 U403 HS0038A2 K403 K401 K402 D401 1N4148 KEY3
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