HarmanKardon-AVR354-avr-sm3维修电路原理图.pdf
《HarmanKardon-AVR354-avr-sm3维修电路原理图.pdf》由会员分享,可在线阅读,更多相关《HarmanKardon-AVR354-avr-sm3维修电路原理图.pdf(79页珍藏版)》请在收音机爱好者资料库上搜索。
1、MK2302S-01MDS 2302S-01 BIntegrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 Multiplier and Zero Delay BufferDescriptionThe MK2302S-01is a high performance Zero Delay Buffer (ZDB) which integrates ICS proprietary analog/digital Phase Locked Loop (PLL) techniques. T
2、he chip is part of ICS ClockBlocksTM family and was designed as a performance upgrade to meet todays higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay
3、 through the device. There are two outputs on the chip, one being a low-skew divide by two of the other output. The MK2302S-01 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphics/video. By allowing off-chip feedback paths, the
4、device can eliminate the delay through other devices.Features8 pin SOIC packageLow input to output skew of 250ps max Absolute jitter 500psPropagation Delay 350psAbility to choose between different multipliers from 0.5X to 16XOutput clock frequency up to 133 MHz at 3.3VCan recover degraded input cloc
5、k duty cycleOutput clock duty cycle of 45/55Full CMOS clock swings with 25mA drive capability at TTL levelsAdvanced, low power CMOS processOperating voltage of 3.3V or 5VIndustrial temperature version availableBlock DiagramPhaseDetector,ChargePump,and LoopFilterdivideby NCLK1External feedback can co
6、me from CLK1 or CLK2 (see table on page 2)ICLKFBINS1:0VCOCLK2/2130AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 Multiplier and Zero Delay BufferMDS 2302S-01 BIntegrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 295-9800 MK2302S-01Pin AssignmentClock Multiplier D
7、ecoding Table 1(Multiplies Input clock by shown amount)Pin DescriptionsFBINICLKGNDVDDS0CLK1CLK212348765GNDS1123487658 pin (150 mil) SOICFBINS1S0CLK1CLK2CLK1002 X ICLKICLKCLK1014 X ICLK2 X ICLKCLK110ICLKICLK/2CLK1118 X ICLK4 X ICLKCLK2004 X ICLK2 X ICLKCLK2018 X ICLK4 X ICLKCLK2102 X ICLKICLKCLK21116
8、 X ICLK8 XICLKPinNumberPinNamePin TypePin Description1FBINInputFeedback clock input.2ICLKInputReference clock input.3GNDPowerConnect to ground.4S0InputSelect 0 for output clock per decoding table above. Pull-up.5S1InputSelect 1 for output clock per decoding table above. Pull up.6CLK1OutputClock outp
9、ut per table above.7VDDPowerConnect to +3.3V or +5.0V.8CLK2OutputClock output per table above. Low skew divide by two of pin 6 clock.131AVR354 harman/kardonharman/kardon RadioFans.CN 收音机爱 好者资料库 Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs ADV7342/ADV7343 Rev. 0 Information furnished by Analog
10、 Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implica
11、tion or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 Fax: 781.461.3113 2006 Analog Devices, Inc. All rights reserved.
12、 FEATURES 74.25 MHz 20-/30-bit high definition input support Compliant with SMPTE 274M (1080i), 296M (720p), and 240M (1035i) 6, 11-bit, 297 MHz video DACs 16 (216 MHz) DAC oversampling for SD 8 (216 MHz) DAC oversampling for ED 4 (297 MHz) DAC oversampling for HD 37 mA maximum DAC output current NT
13、SC M, PAL B/D/G/H/I/M/N, PAL 60 support NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz) Multiformat video input support 4:2:2 YCrCb (SD, ED, and HD) 4:4:4 YCrCb (ED and HD) 4:4:4 RGB (SD, ED, and HD) Multiformat video output support Composite (CVBS) and S-Video (Y/C) Component YPrPb (SD, ED
14、, and HD) Component RGB (SD, ED, and HD) Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant Simultaneous SD and ED/HD operation EIA/CEA-861B compliance support Programmable features Luma and chroma filter responses Vertical blanking interval (VBI) Subcarrier frequency (FSC) and phase Luma delay
15、Copy generation management system (CGMS) Closed captioning and wide screen signaling (WSS) Integrated subcarrier locking to external video source Complete on-chip video timing generator On-chip test pattern generation On-board voltage reference (optional external input) Serial MPU interface with dua
16、l I2C and SPI compatibility 3.3 V analog operation 1.8 V digital operation 3.3 V I/O operation Temperature range: 40C to +85C APPLICATIONS DVD recorders and players High definition Blu-ray DVD players HD-DVD players FUNCTIONAL BLOCK DIAGRAM RGND_IOVDD_IO10-BITSDVIDEODATA20-BITED/HDVIDEODATAS_HSYNCP_
17、HSYNC P_VSYNC P_BLANKS_VSYNC11-BITDAC 1DAC 111-BITDAC 2DAC 211-BITDAC 3DAC 311-BITDAC 4DAC 411-BITDAC 5DAC 511-BITDAC 6DAC 6MULTIPLEXERREFERENCEAND CABLEDETECT16x/4x OVERSAMPLINGDAC PLLVIDEO TIMING GENERATORPOWERMANAGEMENTCONTROLCLKIN (2) PVDDPGND EXT_LF (2) VREFCOMP (2)RSET (2)ED/HD INPUTDEINTERLEA
18、VEPROGRAMMABLEHDTV FILTERSSHARPNESS ANDADAPTIVE FILTERCONTROLYCbCrHDTVTESTPATTERNGENERATORYCbCrTORGB MATRIXG/BRGBASYNCBYPASSRGBDGND (2)VDD (2)SCL/MOSISDA/SCLKALSB/SPI_SSSFL/MISOMPU PORTSUBCARRIER FREQUENCYLOCK (SFL)YUVTOYCrCb/RGBPROGRAMMABLECHROMINANCEFILTERADDBURSTRGB/YCrCbTOYUVMATRIX4:2:2 TO 4:4:4
19、HD DDRDEINTERLEAVESIN/COS DDSBLOCK16FILTER16FILTER4FILTERAGNDVAAADDSYNCVBI DATA SERVICEINSERTIONPROGRAMMABLELUMINANCEFILTER06399-001ADV7342/ADV7343 Figure 1. Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights. Protected by U.S. Patent Numbers 4,631,603, 4
20、,577,216, 4,819,098 and other intellectual property rights. 132AVR354 harman/kardonharman/kardon ADV7342/ADV7343 Rev. 0 | Page 18 of 88 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64GND_IO63CLKIN_B62S761S660S559S458S357DGND56VDD55S254S153S052TEST551TEST450S_HSYNC49S_VSYNC47RSET146VREF45COMP142DAC 34
21、3DAC 244DAC 148SFL/MISO41VAA40AGND39DAC 437DAC 636RSET235COMP234PVDD33EXT_LF138DAC 52TEST03TEST14Y07Y36Y25Y11VDD_IO8Y49Y510VDD12Y613Y714TEST215TEST316C011DGND17C118C219ALSB/SPI_SS20SDA/SCLK21SCL/MOSI2223P_HSYNC24P_VSYNC25P_BLANK26C4C327C528C629C730CLKIN_A3132PGNDPIN 1ADV7342/ADV7343TOP VIEW(Not to S
22、cale)EXT_LF206399-021 Figure 21. Pin Configuration Table 13. Pin Function Descriptions Pin No. Mnemonic Input/ Output Description 13, 12, 9 to 4 Y7 to Y0 I 8-Bit Pixel Port. Y0 is the LSB. Refer to Table 31 for input modes. 29 to 25, 18 to 16 C7 to C0 I 8-Bit Pixel Port. C0 is the LSB. Refer to Tabl
23、e 31 for input modes. 62 to 58, 55 to 53 S7 to S0 I 8-Bit Pixel Port. S0 is the LSB. Refer to Table 31 for input modes. 52, 51, 15, 14, 3, 2 TEST5 to TEST0 I Unused. These pins should be connected to DGND. 30 CLKIN_A I Pixel Clock Input for HD Only (74.25 MHz), ED1 Only (27 MHz or 54 MHz) or SD Only
24、 (27 MHz). 63 CLKIN_B I Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a 74.25 MHz reference clock for HD operation. 50 S_HSYNC I/O SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD horizontal synchronizatio
25、n signal. See the External Horizontal and Vertical Synchronization Control section. 49 S_VSYNC I/O SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control section.
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- HarmanKardon AVR354 avr sm3 维修 电路 原理图