Teac-PD-H500C-Service-Manual电路原理图.pdf
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1、 Compact Disc Player PD-H500C RadioFans.CN 收音机爱 好者资料库 RadioFans.CN 收音机爱 好者资料库 SERVICE MANUAL 3 TC9432AF/ TC9462AF (Digital Signal Processor) PIN No.NAMEI/OFUNCTIONAL DESCRIPTIONREMARKS TEST0 HSO UHSO EMPH LRCK VSS BCK AOUT DOUT MBOV IPF SBOK CLCK VDD VSS DATA SFSY SBSY SPCK SPDA COFS MONIT VDD TESIO
2、0 P2VREF HSSW ZDET PDO TMAXS TMAX With pull-up resistor. - - - - - - - - - - - - - - - - - - - - - - - 2-state output (PVREF,HiZ) - 3-state output (P2VREF,PVREF,VSS) - 3-state output (P2VREF,HiZ,VSS) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Test mode terminal.
3、 Normally, keep at open. Playback speed mode flag output terminal. Subcode Q data emphasis flag output terminal. Emphasis ON at “H” level and OFF at “L” level. The output polarity can invert by command. Channel clock output terminal. (44.1 kHz) L-ch at “L” level and R-ch at “H” level. The output pol
4、arity can invert by command. Digital GND terminal. Bit clock output terminal. (1.4112 MHz) Audio data output terminal. Digital data output terminal. Buffer memory over signal output terminal. Over at “H” level. Correction flag output terminal. At “H “ level, AOUT output is made to correction impossi
5、bility by C2correction processing. Subcode Q data CRCC check adjusting result output terminal. The adjusting result is OK at “H” level. Subcode PW data readout clock input/outputtermi- nal. This terminal can select by command bit. Digital power supply voltage terminal. Digital GND terminal. Subcode
6、PW data output terminal. Playback frame sync signal output terminal. Subcode block sync signal output terminal. Processor status signal readout clock output terminal. Processor status signal output terminal. Correction frame clock output terminal. (7.35 kHz) Internal signal (DSP internal flag and PL
7、L clock) output terminal. Selected by command. Digital power supply voltage terminal. Test input/output terminal. Normally, keep at “L” level. PLL double reference voltage supply terminal. 2/4 times speed at “VREF” voltage. 1 bit DA converter zero detect flag output terminal. Phase difference signal
8、 output terminal of EFM signal and PLCK signal. TMAX detection result output terminal. Selected by command bit (TMPS). TMAX detection result output terminal. Selected by command bit (TMPS). - O O O O - O O O O O O I/O - - O O O O O O O - I - O O O O O UHSOHSOPLAYBACK SPEED HHNormal HL2 times LH4 tim
9、es LL- DIFFERENCE RESULTTMAX OUTPUT Longer than fixed ferq.“P2VREF” Shorter than fixed freq.“VSS” Within the fixed freq.“HiZ” SERVICE MANUAL 5 PIN No.NAMEI/OFUNCTIONAL DESCRIPTIONREMARKS DMOUT CKSE DACT TESIN TESIO1 VSS PXI PXO VDD XVSS XI XO XVDD DVSR RO DVDD DVR LO DVSL TEST1 TEST2 TEST3 BUS0 BUS1
10、 BUS2 BUS3 VDD VSS BUCK CCE TEST4 TSMOD RST With pull-up resistor. With pull-up resistor. With pull-up resistor. Analog input. Analog input. - - - - - - - - - - - - - With pull-up resistor. With pull-up resistor. With pull-up resistor. Schmit input. With pull-up resistor. - - Schmit input. Schmit in
11、put. With pull-up resistor. With pull-up resistor. With pull-up resistor. 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 This terminal controls IO0IO3 terminal. At “L” level time, IO0, 1 out feed equalizer signal of 2-state PWM. IO2, 3 out disk eq
12、ualizer signal of 2-state PWM. Normally, keep at open. DAC test mode terminal. Normally, keep at open. Test input terminal. Normally, keep at “L” level. Test input/output terminal. Normally, keep at “L” level. Digital GND terminal. Crystal oscillator connecting input terminal for DSP. Normally, keep
13、 at “L” level. Crystal oscillator connecting output terminal for DSP. Digital power supply voltage terminal. Oscillator GND terminal for system clock. Crystal oscillator connecting input terminal for system clock. Crystal oscillator connecting output terminal for sys- tem clock. Oscillator power sup
14、ply voltage terminal for system clock. Analog GND terminal for DA converter. (R-ch) R channel data forward output terminal. Analog supply voltage terminal for DA converter. Reference voltage terminal for DA converter. L channel data forward output terminal. Analog GND terminal for DA converter. (L-c
15、h) Test mode terminal. Normal, keep at open. Test mode terminal. Normal, keep at open. Test mode terminal. Normal, keep at open. Micom interface data input/output terminal. Digital Ppower supply voltage terminal. Digital GND terminal. Micom interface clock input terminal. Command and data sending/re
16、ceiving chip enable sig- nal input terminal.The bus line becomes active at “L” level. Test mode terminal. Normal, keep at open. Local test mode selection terminal. Reset signal input terminal. Reset at “L” level. I I I I I - I O - - I O - - O - - O - I I I I/O I/O I/O I/O - - I I I I I 6 SERVICE MAN
17、UAL 1 100 99 Micom Interface LPF 1bit DAC Clock generator Correction circuit 16K RAM Address circuit Digital out Sub code decoder PLL TMAXData slicer A / D VCO CLV servo RAM ROM Digital equalizer Servo control PWMD / A Automatic adjustment circuit Status Synchronous guarantee EFM decode Audio out ci
18、rcuit TEST 0 HSO UHSO EMPH LRCK VSS BCK AOUT DOUT MBOV IPF SBOK CLCK VDD VSS DATA SFSY SBSY SPCK SPDA COFS MONIT VDD TESIO 0 P2VREF HSSW ZDET PDO TMAXS TMAX XVDD XO XI XVSS VDD PXO PXI VSS TES I/N TES IO1 DACT CKSE DMOUT IO3 IO2 IO1 IO0 VSS VDD FLGD FLGC FLGB FLGA SEL 2VREF DM/O FVO FMO TEBC RFGC LP
19、FN LPFO PVREF VCOREF VCOF AVSS SLCO RF1 AVDD RFCT RFZI RFRP EF1 SBAD TSIN TEI TEZI FOO TRO VREF RST TSMOD TEST4 CCE BUCK VSS VDD BUS3 BUS2 BUS1 BUS0 TEST3 TEST2 TEST1 DVSL LO DVR DVDD RO DVSR 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 234 80797877767574737271706968676665646362616059585756
20、5554535251 567891011121314151617181920212324222627252930 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 28 SERVICE MANUAL 7 PIN No. SYMBOLI/OFUNCTION DESCRIPTIONREMARKS Power supply input terminal. RF amplitude adjustment control signal input termi- nal. Controlled by 3-PWM signals. (PW
21、M carrier = 88.2kHz) Open loop gain adjustment terminal for AGC amp. Main beam l-V amp input terminal. Main beam l-V amp input terminal. Sub beam l-V amp input terminal. Sub beam l-V amp input terminal. Monitor photo diode amp input terminal. Laser diode amp input terminal. Laser diode control signa
22、l input terminal and APC circuit ON/OFF control signal terminal. Tracking error balance adjustment signal input ter- minal. Controlled by 3-PWM signal. (PWM carrier = 88.2 kHz) Reference voltage (2VRO) output terminal. 2VRO = 4.2 V when Vcc = 5 V TE amp negative input terminal. TE error signal outpu
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