Alinco_DJ-195_serv.pdf
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1、DJ-195 Service Manual CONTENTS SPECIFICATIONS 1) GENERAL . 2 2) TRANSMITTER . 2 3) RECEIVER . 2 CIRCUIT DESCRIPTION 1) Receiver System . 3, 4 2) Transmitter System. 4 3) PLL Synthesizer Circuit . 4, 5 4) CPU and Peripheral Circuits . 5, 6 5) M3826M8L*GP (XA0644). 68 SEMICONDUCTOR DATA 1) NMJ2070M T1
2、 (XA210) . 9 2) AT24C16N-10SI-2.7TER (XA0368) . 9 3) M5222FP-600C (XA0385) . 10 4) TK14521MTL (XA0515). 11 5) M64082AGP (XA0543). 12 6) NJM2904V-TE1 (XA0573) . 12 7) NJM2902V-TE1 (XA0596) . 12 8) S-81250SG-QD-T1 (XA0619). 13 9) S-80845ALMP-EA9-T2 (XA0620) . 13 10) Transistor, Diode, and LED Ontline
3、Drawings . 14 11) LCD Connection (EL0044) . 14 EXPLODED VIEW 1) Front View. 15 2) Rear View . 16 PARTS LIST MAIN Unit . 1719 Mechanical Parts . 20 Packing Parts . 20 ADJUSTMENT 1) Required Test Equipment. 21, 22 2) Adjustment Mode . 2326 PC BOARD VIEW MAIN Unit . 27 SCHEMATIC DIAGRAM. 28 BLOCK DIAGR
4、AM. 29 ALINCO,INC. 2 SPECIFICATIONS 1) GENERAL Frequency coverageT: TX 144 147.995MHzRX 135 173.995MHz E: TX 144 145.995MHzRX 144 145.995MHz EAH : TX 135 173.995MHzRX 135 135.995MHz TFH : TX 150 173.995MHzRX 135 173.995MHz TLH : TX 150 173.995MHzRX 135 173.995MHz ModeF3E (FM) Channel steps5,10,12.5,
5、15,20,25, one amplifier (pins 5, 6, and 7) is composed of pre- emphasis and IDC circuits and the other (pins 1, 2, and 3) is composed of a splatter filter. The maximum frequency deviation is obtained by VR202 and input to the cathode of the varicap of the VCO, to change the electric capacity in the
6、oscillation circuit. This produces the frequency modulation. 2. Power Amplifier Circuit The transmitted signal is oscillated by the VCO, amplified by the pre-drive amplifier (Q4) and drive amplifier (Q3), and input to the final amplifier (Q2). The signal is then amplified by the final amplifier (Q2)
7、 and led to the antenna switch (D1) and low-pass filter (L5, L4, L3, L2, C16, C15, C14 and C13), where un- wanted high harmonic waves are reduced as needed, and the resulting signal is supplied to the antenna. 3. APC Circuit Part of the transmission power from the low-pass filter is detected by D6,
8、con- verted to DC, and then amplified by a differential amplifier. The output voltage controls the bias voltage from the source of Q2 and Q3 to maintain the trans- mission power constant. 3) PLL Synthesizer Circuit 1. PLL The dividing ratio is obtained by sending data from the CPU (IC9) to pin 2 and
9、 sending clock pulses to pin 3 of the PLL IC (IC1). The oscillated signal from the VCO is amplified by the buffer (Q5) and input to pin 6 of IC1. Each program- mable divider in IC1 divides the frequency of the input signal by N according to the frequency data, to generate a comparison frequency of 5
10、 or 6.25kHz. 2. Reference Frequency Circuit The reference frequency appropriate for the channel steps is obtained by divid- ing the 21.25MHz reference oscillation (X1) by 4250 or 3400, according to the data from the CPU (IC9). When the resulting frequency is 5kHz, channel steps of 5, 10, 15, 20, 25,
11、 30, and 50kHz are used. When it is 6.25kHz, the 12.5kHz channel step is used. 5 3. Phase Comparator Circuit The PLL (IC1) uses the reference frequency, 5 or 6.25kHz. The phase com- parator in the IC1 compares the phase of the frequency from the VCO with that of the comparison frequency, 5 or 6.25kH
12、z, which is obtained by the internal divider in IC1. 4. PLL Loop Filter Circuit If a phase difference is found in the phase comparison between the reference frequency and VCO output frequency, the charge pump output (pin 8) of IC1 generates a pulse signal, which is converted to DC voltage by the PLL
13、 loop filter and input to the varicap of the VCO unit for oscillation frequency control. 5. VCO Circuit A Colpitts oscillation circuit driven by Q1 directly oscillates the desired fre- quency. The frequency control voltage determined in the CPU (IC9) and PLL circuit is input to the varicaps (D32 and
14、 D34). This change the oscillation fre- quency, which is amplified by the VCO buffer (Q5) and output from the VCO unit. 4) CPU and Peripheral Circuits 1. LCD Display Circuit The CPU turns ON the LCD via segment and common terminals with 1/4 the duty and 1/3 the bias, at the frame frequency is 112.5H
15、z. 2. Display Lamp Circuit When the LAMP key is pressed, “H” is output form pin 50 of CPU (IC9) to the bases of Q12. Q12 then turn ON and the LEDs (D12 and D17) light. 3. Reset and Backup When the power form the DC jack or external battery increases from Circuits 0 V to 2.5 or more, “H” level reset
16、signal is output form the reset IC (IC11) to pin 33 of the CPU (IC9), causing the CPU to reset. The reset signal, however, waits at 100, and does not enter the CPU untilthe CPU clock (X2) has stabi- lized. 4. S(Signal) Meter Circuit The DC potential of pin 8 of IC5 is input to pin 1 of the CPU (IC9)
17、, converted from an analog to a digital signal, and displayed as the S-meter signal on the LCD. 5. DTMF Encoder The CPU (IC9) is equipped with an internal DTMF encoder. The DTMF signal is output from pin 10, through R102 and R158 (for level adjust-ment), and then through the microphone amplifier (IC
18、7), and is sent to the varicap of the VCO for modulation. At the same time, the monitor-ing tone passes through the AF circuit and is output form the speaker.6. CTCSS Encoder The CPU (IC9) is equipped with an internal tone encoder. The tone signal (67.0 to 250.3 Hz) is output form pin 9 of the CPU t
19、o the varicap (D3) of the VCO for modulation. 6 6. Tone Encoder The CPU (IC9) is equipped with an internal tone encoder.The tone signal (67.0 to 250.3Hz) is output from pin 9 of the CPU to the varicap (D3) of the VCO for modulation. 7. DCS Encoder The CPU (IC9) is equipped with an internal DCS code
20、encoder. The code (023 to 754) is output from pin 9 of the CPU to the varicap (D3) of the PLL reference oscillator. When DCS is ON, DCS MUTE circuit (Q15-ON, Q18-ON, Q16-OFF) works. The modulation activates in X1 side only. 8. CTCSS, DCS Decoder The voice band of the AF output signal from pin 10 of
21、IC5 is cut by sharp active filter IC8 (VCVS) and amplified, then led to pin 4 of CPU. The input signal is compared with the programmed tone frequency code in the CPU. The squelch will open when they match. 9. Clock Shift In the unlikely event that CPU clock noise is present on a particular operating
22、 frequency programmed into the radio, you can shift the CPU clock frequency to avoid the CPU clock-noise. The output signal from pin 31 of the CPU turns on Q30. Then the oscillation frequency of X2 will be shifted about 300 ppm. 5) M3826M8L*GP (XA0644) CPU Terminal Connection (TOP VIEW) 7 No.Pin Nam
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