djx3_SM.pdf

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1、DJ-X3 Service Manual CONTENTS SPECIFICATIONS 1) GENERAL . 2 2) RECEIVER . 2 CIRCUIT DESCRIPTION 1) Receiver . 36 2) M38224M6M(E:XA0862, T:XA0836) . 7 3) Terminal function of CPU . 8 SEMICONDUCTOR DATA 1) uPD3140GS-E1 (XA0312) . 9 2) TC4W53FU (XA0348). 10 3) NJM2904V (XA0573). 10 4) CXA1622M/P (XA078

2、7). 10 5) MB88347LPFV-G-BND-EF (XA0599) . 11 6) TK11816M (XA0665) . 12 7) TK10931V (XA0666). 12 8) TA4101FTE12L (XA0667) . 13 9) S-80828ALNP-EAR-T2 (XA0834) . 13 10) BR24C64F-E2 (XA0669) . 14 11) S-81230SG-QB-X (XA0833) . 14 12) uPC2757T-E3 (XA0743) . 15 13) TC7SET08FU (XA0586) . 15 14) LA3335M (XA0

3、786) . 16 15) NJM2107 (XA0850) . 17 16) Transistor, Diode and LED Outline Drawings. 17 17) LCD Connection . 18 EXPLODED VIEW 1) Front View. 19 2) Bottom View. 20 PARTS LIST MAIN Unit . 2126 SW Unit . 26 Mechanical Parts . 26 Packing. 26 ADJUSTMENT 1) How to enter the adjustment mode . 27 2) Adjustme

4、nt . 2729 PC BOARD VIEW. 3031 SCHEMATIC DIAGRAM. 32 BLOCK DIAGRAM. 33 ALINCO,INC. 2 SPECIFICATIONS 1) GENERAL Receiving rangeE: 0.1 1299.995 MHz T: 0.1 823.995 MHz 850.000 868.995 MHz 895.000 1299.995 MHz Modulation modeFM, WFM, AM Ant. impedance50 Ant. terminalSMA Supply voltageDC 3.6V 6V (Internal

5、 battery) DC 4.5V 16V (external regulated source) GroundNegative ground Current consumptionreception : approx.75mA Battery save (1:4)approx.39mA Temperature range-10 +60C (+14 +140 F) Frequency stability5ppm(-10 +60C)(+14 +140F) Dimension56(W) 102(H) 23(D)mm WeightApprox.145g 2) RECEIVER SystemTripl

6、e-conversion superheterodyne First IF248.45 MHz Second IF38.85 MHz Third IF450 kHz SelectivityAM/FM -6dB/12kHz or over , -60dB/30kHz or less WFM-6dB/150kHz or over SensitivityFM/WFM 12dB SINAD, AM 10dB S/N Typ.AM: 0.5 1.62MHz17dBu10dB S/N 1.625MHz or over5dBu10dB S/N FM: 30 550MHz-3dBu12dB SINAD 550

7、MHz or over0dBu12dB SINAD WFM: 76 770MHz13dBu12dB SINAD Audio output power more than 220mW (8) 3 CIRCUIT DESCRIPTION 1) Receiver 1. RX Method: Triple Super Heterodyne Method 1st IF.:248.45MHz 2nd IF.:38.85MHz 3rd IF.:450KHz 2. Front End 0.1 29.995MHz The signal input from antenna is switched at band

8、 switch D19, passing through the low pass filter, it is amplified at RF amplifier Q15. Then the signal is added to the 1st mixer IC3 through the band switch D17. 30 136.995MHz The signal input from antenna is switched at band switch D23, passing through the band pass filter, it is amplified at RF am

9、plifier Q21. Then the signal is added to the 1st mixer IC3 through the band switch D22. 137 222.995MHz The signal input from antenna is switched at band switch D27, passing through the band pass filter, it is amplified at RF amplifier Q23. Then the signal is added to the 1st mixer IC3 through the ba

10、nd switch D26. 223 367.995MHz The signal input from antenna is switched at band switch D29, passing through the band pass filter, it is amplified at RF amplifier Q27. Then the signal is added to the 1st mixer IC3 through the band switch D28. 368 469.995MHz The signal input from antenna is switched a

11、t band switch D32, passing through the band pass filter, it is amplified at RF amplifier Q32. Then the signal is added to the 1st mixer IC3 through the band switch D31. 470 129.995 MHz The signal input from antenna is switched at band switch D37 and D45, passing through the band pass filter, it is a

12、mplified at RF amplifier Q38. Then the signal is added to the 1st mixer IC3 through the band switch D36. 3. Mixer The 1st Mixer The input signal and the 1st local signal is added or subtracted at mixer IC3, and SAW filter FL1 selects the signal of 248.45 MHz, then eliminates the adjacent signal. 4 T

13、he 2nd Mixer The input signal and the 2nd local signal is added or subtracted at mixer IC4, and switched to FM/AM receiving side or WFM receiving side at D24 or D25 . FM/AM At FM/AM receiving side, the crystal filter XF1 selects the signal of 38.85 MHz. The signal is amplified at the 1st IF amplifie

14、r Q22 after the adjacent signal is eliminated. WFM At WFM receiving side, the band pass filter selects the signal of 38.85 MHz. The signal is amplified at the 1st IF amplifier Q22 after the adjacent signal is eliminated. 4. IF FM/AM The amplified signal at the 1st IF amplifier Q22 is supplied to pin

15、 24 of IC6 for demodulation. The signal of 12.8 MHz from the IC 1 reference buffer output is multiplied by 3 at Q17, then mixed with the signal added to pin 1 of IC6 in the mixer circuit inside IC6 to be converted into the 2nd IF signal of 450 kHz. The converted 2nd IF signal is output from pin 3 of

16、 IC6. FM The output signal from pin 3 of IC6 is input to pin 7 of IC6 after the adjacent signal is eliminated at the ceramic filter FL2. The 2nd IF signal input to pin 7 of IC6 is demodulated at the limiter amplifier and quadrature detection circuit inside IC. Then the signal is output from pin 12 o

17、f IC6 as an AF signall. AM The output signal from pin 3 of IC6 is input to pin 5 of IC6 after the adjacent signal is eliminated at the ceramic filter FL2. The 2nd IF signal input to pin 5 of IC6 is output from pin 13 of IC6 as an AF signal after AM is detected inside IC. Also reverse AGC is added to

18、 the 1st IF amplifier Q22 by AGC amplifier Q25 and the gain is controlled to get the normal audio output even though the input signal is fluctuated. WFM The output signal from pin 3 of IC6 is input to pin 7 of IC6. The 2nd IF signal input to pin 7 of IC6 is demodulated at the limiter amplifier and q

19、uadrature detection circuit inside IC, and output from pin 12 of IC6 as an AF signal. 5. Squelch The AF signal is output from pin 12 of IC6 and input to pin 19 of IC6. The input signal is output from pin 21 of IC6 through the noise filter amplifier and rectifying circuit. The rectified signal is sup

20、plied to the A/D port of microcomputer IC1. Then the microcomputer IC1 judges the signal to control ON/OFF of audio output. 5 6. Audio FM/AM/WFM The audio output signal for receiving FM/WFM and AM is switched at IC9. The output audio signal is input to pin 1 of IC13 of stereo multiplex demodulator t

21、hrough AF amplifier IC17. When the input audio signal doesnt have a pilot signal, each audio signal is output from pin 9 and pin 10 to pin 1 and pin 16 of the audio amplifier IC14 equipped with the electronic volume. After the volume is adjusted, the signal is output from pin 7 and pin 10 to drive t

22、he speaker, etc. When the input signal has a pilot signal, each audio signal is output; L side signal is output from pin 9, and R side signal is output from pin 10. Then the signals are input to the audio amplifier IC 14 equipped with electronic volume; L side signal is input to pin 1 and R side sig

23、nal is input to pin 16. After adjusting the volume the signals are output; the L side from pin 7 and the R side from pin 10 to drive the speaker, etc. 7. VCO The 1st Local VCO for the 1st local consists of the Colpitts oscillator. D15, D16 and L4 determine the frequency, and the signal is oscillated

24、 at the transistor Q9. The oscillated signal is supplied to pin 2 of PLL-IC1 passing through the buffer amplifier Q11 and Q10. The 2nd Local VCO for the 2nd local consists of the Colpitts oscillator. D20, D21 and L15 determine the frequency, and the signal is oscillated at the transistor Q19. The os

25、cillated signal is supplied to pin 19 of PLL-IC1 passing through the buffer amplifier Q20. 8. PLL PLL-IC1 is used to control the oscillating frequency of VCO. IC1 is controlled by the serial control signal sent from the microprocessor IC7. The reference frequency of 12.8 MHz is generated by oscillat

26、ing the crystal oscillator X1 inside the circuit. The 1st Local IC1 compares the frequency gained by dividing the signal added to pin 2 of IC1 by the control signal from IC7 with the frequency gained by dividing the reference frequency of 12.8 MHz inside IC1. When the phase difference is found as a

27、result of phase comparison, the pulse signal is output from the charge pump output of pin 8 of IC1, then the signal is converted into the DC voltage at the active filter Q13 and Q14 and added to the cathode side of VCO 6 vari-cap D15 and D16 to make the phases equal. In result the stabilized oscilla

28、tion can be done at the desired frequency. The 2nd Local IC1 compares the frequency gained by dividing the signal added to pin 19 of IC1 by the control signal from IC7 with the frequency gained by dividing the reference frequency of 12.8 MHz inside IC1. When the phase difference is found as a result

29、 of phase comparison, the pulse signal is output from the charge pump output of pin 13 of IC1, then the signal is converted into the DC voltage at the inside circuit for active filter and added to the cathode side of VCO vari-cap D20 and D21 to make the phases equal. In result the stabilized oscilla

30、tion can be done at the desired frequency. 7 2) M38224M6M (E:XA0862, T:XA0836) CPU Terminal Connection (TOP VIEW) 8 3) Terminal function of CPU No. TerminalSignalI/ODescription 1AN7BATADBattery input 2P66S/MOStereo / Monophonic 3P65RESWIR/E push key 4AN4SQLADSquelch input 5AN3SMTADS-meter input 6P62

31、AFPCOAF power supply 7P61BND3OBand3 SW 8P60BND6OBand6 SW 9P57BND2OBand2 SW 10P56BND4OBand4 SW 11P55BND5OBand5 SW 12P54BND1OBand1 SW 13P53ABAROAntenna SW 14P52SBAROAntenna SW 15INT3RE2IRotary encoder input 16P50RE1IRotary encoder input 17P47RCORX SW 18P46ASWOAntenna SW 19TXDCTXOClone TX 20RXDCRXIClon

32、e RX 21 P43/INT1PSWIPower key 22INT0BUIBackup interrupt 23P41BEEPOBeep output 24P40JKDTIJack state input 25RESETRSTIReset interrupt 26P71SCKOEEPROM clock 27P70SDAI/OEEPROM data 28XINXINIClock input 29XOUTXOUTOClock output 30VSSVSSGND 31P27SW2IKey input 32P26SW3IKey input 33P25SW4IKey input 34P24SW30

33、1IKey input 35P23SW302IKey input 36P22 CLNSW OClone SW 37P21STB2ODAC strobe 38P20DATAI/OData / Unlock 39SEG22SEG22 40SEG21SEG21 NoTerminalSignalI/ODescription 41SEG20SEG20 42SEG19SEG19 43SEG18SEG18 44P12DBCODoubler SW 45P11C3COCommon power SW 46P10SCTOSecret signal output 47P07AFSOAF SW 48P06CLKOClo

34、ck 49P05STB1OPLL strobe 50P04PLLCOPLL power supply 51P03P1COPLL 1ch SW 52P02P2COPLL 2ch SW 53SEG17SEG17 54SEG16SEG16 55SEG15SEG15 56SEG14SEG14 57SEG13SEG13 58SEG12SEG12 59SEG11SEG11 60SEG10SEG10 61SEG9SEG9 62SEG8SEG8 63SEG7SEG7 64SEG6SEG6 65SEG5SEG5 66SEG4SEG4 67SEG3SEG3 68SEG2SEG2 69SEG1SEG1 70SEG0

35、SEG0 71VCCVDD 72VREFVDD 73AVSSGND 74COM3COM3 75COM2COM2 76COM1COM1 77COM0COM0 78VL3VL3 79VL2VL2 80VL1VL1 9 SEMICONDUCTOR DATA 1) uPD3140GS-E1 (XA0312) 80 550MHz Dual PLL Synthesizer Specifications Operating frequency:200 400MHz (Vin=-12 -0dBm, pin 2 and 19 input) 80 550MHz (Vin=-8 -0dBm, pin 2 and 1

36、9 input) Consumption current:2.7 4.1mA (Vcc=1.8V while 1 channel is used) 4.3 6.6mA (Vcc=1.8V while both channels are used) 0 10uA (Vcc=1.8V in power save mode) 3.5 5.3mA (Vcc=5V while 1 channel is used) 5.6 8.6mA (Vcc=5V while both channels are used) Operationg voltage:1.8 5.5V 10 2) TC4W53FU (XA03

37、48) 3) NJM2904V (XA0573) Dual Single Supply Operational Amplifer 4) CXA1622M/P (XA0787) IN2 SW2 1 NC NF24 3 GND P GND26 5 OUT2 RIPPLE8 7 15 16 13 14 11 12 9 10 IN1 REG VOL NF1 GND P GND1 OUT1 Vcc Pin AssignmentBlock Diagram 12345678 161514131211109 REGVOL PRE+POWER1 PRE+POWER2 11 5) MB88347LPFV-G-BN

38、D-EF (XA0599) D/A converter for digital tuning 12 6) TK11816M (XA0665) 6 5 4 1 2 3 VIN DK VOUT Pin Assignment Block Diagram 5 6 4 12 3 VIN GND OSC DK VOUT T1 Feed back control Ref. Voltage Start-up Circuit Oscillator VIN OSC DK 7) TK10931V (XA0666) 123456789101112 242322212019181716151413 AM DET RSS

39、I RECT COMP AMP AGC Vref Vcc AM AMP FM AMP FM DET MIXER OSC RF INPUT GND COMP OUTPUT COMP INPUT NOISE AMP OUTPUT NOISE AMP INPUT AM AGC INPUT AGC AMP OUTPUT RF AGC OUTPUT RSSI OUTPUT AM SW AM DET OUT OSC(B) OSC(E) MIX OUTPUT Vcc AM IF INPUT DECOUPLING FM IF INPUT DECOUPLING DECOUPLING LIM OUTPUT QUA

40、D INPUT FM DET OUTPUT Pin Assignment / BLOCK Diagram (Top View) 13 8) TA4101F TE12L (XA0667) 1234 8765 1. IF OUT 2. Vcc 3. OSC IN 4. BASE 5. BASE 6. BASE 7. GND 8. COLLECTOR Pin AssignmentBlock Diagram 23 R1 RB1 RB2 RB3 RB4 R2 R3 Q1Q2Q3Q4 Q5R4Q6 3 RE1RE2 8 1 4 6 7 RL1RL2 9) S-80828ALNP-EAR-T2 (XA083

41、4) 12 34 1 OUT 2 VDD 3 NC 4 VSS Top view Pin Assignment Block Diagram VDD VCC OUT VREF 14 10) BR24C64F-E2 (XA0669) 1 2 3 4 A0 A1 A2 GND Vcc WP SCL SDA 8 7 6 5 13bit 8bit 64Kbit EEPROM ARRAY ADDRESS DECODER SLAVEWORD ADDRESS REGISTER DATA REGISTER CONTROL CIRCUIT VOLTAGE DETECTOR HIGH VOLTAGE GENERAT

42、OR 13bit ACK STOPSTART Block Diagram Pin Assignment VccWPSCLSDA A0A1A2GND BR24C64/F 11) S-81230SG-QB-X (XA0833) Pin AssignmentBlock Diagram VIN VOUT RL 15 12)uPC2757T-E3 (XA0743) 3 2 1 4 5 6 Terminal Connection Block Diagram C1X (Top View) 4 5 6 3 2 1 (Bottom View) 1: RF input 2: GND 3: Lo input 4:

43、PS (Power Save) 5: Vcc 6: IF output RF input IF output Lo input VccGND POWER SAVE 13) TC7SET08FU (XA0586) G 2 1 2 3 5 4 IN B IN A GND Vcc OUT Y Pin AssignmentBlock Diagram 16 14)LA3335M (XA0786) Block Diagram 109 Pin Assignment 876 54321 1: Input 2: PLL loop filter 3: Power supply 4: VCO 5: NC 6 : G

44、ND 7 : Stereo indicator fillter 8 : Pilot sync detection 9 : Decoder output (low) 10 : Decoder output (high) 10 9 8 7 6 1 2 3 4 5 DECODER STEREO SWITCH FF90FF1/2 PHASE COMPARATOR V.C.O FF0 SYNCHNOUS DETECTOR LAMP TRIGGER VCOSTOP 17 15) NJM2107 (XA0850) Pin Assignment Block Diagram 16) Transistor, Diode and LED Outline Drawings TX N MC3 K B L L M 2 Y RV Y K Y 6 RO 3 G13 1SV308(TPH3) XD0339 MA2S728-TX XD0315 DAN235E-TL XD0320 MA2S357-TX XD0337 ISS3