Baofeng_UV-3R_RDA-1846_prog.pdf

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1、 RDA1846 RDA1846 Programming Guide The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. 1 RDA1846 The information contained herein is the exclusive property of RDA and sha

2、ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. 2 Contents Document overview. 4 Doc. A: Interface. 5 1. I2C Interface .5 2 Three- wire SPI interface.7 3. Four- wire SPI interface.8 Doc. B: Programming guide. 9 1. Setting frequency.9 2. Set

3、ting RF band.9 3. Reference clock.9 4. Setting Tx and Rx.10 5. Deep sleep .10 6. TX voice channel.10 7. TX Pa_bias output voltage.11 8. Subaudio.11 9. SQ.12 10. VOX.13 11. Eliminating tail noise.13 12. DTMF.13 13. Tx FM deviation.15 14. Rx voice range.16 RDA1846 The information contained herein is t

4、he exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. 3 15. TX and RX code.16 16. GPIO.16 17. INT.17 18. St_mode.18 19. Pre-emphasis/De-emphasis filter.20 20. Only read register .20 21. Flag.21 22. Initial pro

5、cess.21 23. Register introduction.21 Change List. 25 Disclaimer. 26 RDA1846 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. 4 Document overview This programming guide

6、 has been restructured from previous revisions for clarity. This contains two documents for interface and programmer separately. Interface document contains I2C interface, 3 wire SPI interface and 4 wire SPI interface .Programmer document contains a complete programming guide for using any interface

7、. RDA1846 Doc. A: Interface RDA1846 each register write is 24-bit long, including a r/wbit,7-bit register address , and 16-bit data (MSB is the first bit). R/W A6:0 D15:0 Note If register address is more than 7FH, first write 0 x0001 to 7FH, and then write value to the address subtracted by 80H. Fin

8、ally write 0 x0000 to 7FH Example: writing 85H register address is 0 x001F . Move 7FH 0 x0001; Move 05H 0 x001F; 05H=85H-80H Move 7FH 0 x0000; 1. I2C Interface RDA1846 enable software programming through I2C interface. Software controls chip working states, such as Txon or Rxon operation, and reads

9、status register to get operation result through I2C interface. It includes two pins: SCLK and SDIO. A I2C interface transfer begins with START condition, a command byte and data bytes, each byte has a followed ACK (or NACK) bit, and ends with STOP condition. The command byte includes a 7-bit chip ad

10、dress and a r/wbit. The 7-bit chip address is 7b0101110 when SEN is high, or is 71110001 when SEN is low.The ACK ( or NACK) is always sent out by receiver. When in write transfer, data bytes is written out from MCU, and when in read transfer, data bytes is read out from RDA1846. Figure 1. I2C Interf

11、ace Write Timing Diagram The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. 5 RDA1846 Figure 2. I2C Interface Read Timing Diagram Figure 3 I2C Interface Write Combined F

12、ormat Figure 4 I2C Interface Read Combined Format Table 2. I2C Timing Characteristics PARAMETER SYMBOLTEST CONDITIONMIN TYP MAX UNIT SCLK Frequency fscl 0 - 400 KHz SCLK High Time thigh 0.6 - - s SCLK Low Time tlow 1.3 - - s Setup Time for START Condition tsu:sta 0.6 - - s Hold Time for START Condit

13、ion thd:sta 0.6 - - s Setup Time for STOP Condition tsu:sto 0.6 - - s SDIO Input to SCLK Setup tsu:dat 100 - - ns SDIO Input to SCLK Hold thd:dat 0 - 900 ns STOP to START Time tbuf 1.3 - - s SDIO Output Fall Time tf:out 20+0.1Cb- 250 ns SDIO Input, SCLK Rise/Fall Time tr:in / tf:in 20+0.1Cb- 300 ns

14、Input Spike Suppression tsp - - 50 ns SCLK, SDIO Capacitive Loading Cb - - 50 pF Digital Input Pin Capacitance 5 pF The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. 6

15、RDA1846 2 Three- wire SPI interface RDA1846 enable software programming through three-wire(SPI) interface. Software controls chip working states, such as Txon or Rxon operation, and reads status register to get operation result through three-wire interface. Three-wire interface is slave interface. I

16、t includes three pins: SEN, SCLK and SDIO. SEN and SCLK are input pins , SDIO are bi-direction pins. RDA1846 samples command byte and data at posedge of SCLK.The turn around cycle between command byte from MCU and data from RDA1846 is a half cycle. RDA1846 samples command byte at posedge of SCLK, an

17、d output data also at posedge of SCLK. Figure5. Three-wire Interface Write Timing Diagram Figure6. Three-wire Interface Read Timing Diagram The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior writt

18、en permission of RDA. 7 RDA1846 Table 2. Three-wire Timing Characteristics PARAMETER SYMBOLTEST CONDITIONMIN TYP MAX UNIT SCLK Cycle Time tCLK 35 ns SCLK Rise Time tR 50 ns SCLK Fall Time tF 50 ns SCLK High Time tHI 10 ns SCLK Low Time tLO 10 ns SDIO Input, SEN to SCLK Setup ts 10 - - ns SDIO Input,

19、 to SCLK Hold th 10 - - ns SCLK to SDIO Output Valid tcdv Read 2 - 10 ns SEN to SDIO Output High Z tsdz Read 2 - 10 ns Digital Input Pin Capacitance 5 pF 3. Four- wire SPI interface RDA1846 enable software programming through four-wire(SPI) interface. Software controls chip working states, such as T

20、xon or Rxon operation, and reads status register to get operation result through four-wire interface. Four-wire interface is slave interface. It includes four pins: SEN, SCLK , SDI and SDO. SEN,SCLK and SDI are input pins , SDO are bi-direction pins. The information contained herein is the exclusive

21、 property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. 8 RDA1846 Figure7. Four-wire Interface Write/Read Timing Diagram The information contained herein is the exclusive property of RDA and shall not be distributed, reprod

22、uced, or disclosed in whole or in part without prior written permission of RDA. 9 RDA1846 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. 9 Doc. B: Programming guide

23、1. Setting frequency Bit Name Function 29H13:0 freq Freq high value (unit 1khz/8) 2aH15:0 freq Freq low value (unit 1khz/8) Freq= Binary (Freq(MHz)*1000*8) Such as frequency is 409.75MHz, Freq=409.75*1000*8=3278000= Binary (1100100000010010110000) so write 29H 15:0 =000000000000110010 and 2aH 15:0 =

24、 0000010010110000. 2. Setting RF band Bit Name Function 0fH7:6 band_select 00 = 400520MHz 10 =200260MHz 11 = 134174MHz 3. Reference clock RDA1846 takes 12MHz14MHz or 24MHz 28 MHz crystals as its master reference clock. Setting 2bH15:0, 2cH15:0 and 04H0 according different reference clock. Bit Name F

25、unction 2bH15:0 xtal_freq Crystal clk freq (unit khz) 1214MHz:crystal freq*1000 24 28MHz: (crystal freq/2)*1000 2cH15:0 adclk_freq Adc clk freq (unit khz) 1214MHz:(crystal freq/2)*1000 24 28MHz: (crystal freq/4)*1000 04H0 clk_mode 1214MHz:1 24 28MHz:0 Such as 12.8M crystal (12MHz14MHz) RDA1846 The i

26、nformation contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. 10 2bH15:0= xtal_freq=12.8*1000=12800 2cH12:0 =adclk_freq=(12.8/2)*1000=6400 04H0= clk_mode =1 26M crystal (24MHz28MHz) 2bH

27、15:0= xtal_freq=(26/2)*1000=13000 2cH15:0 =adclk_freq=(26/4)*1000=6500 04H0= clk_mode =0 4. Setting Tx and Rx Bit Name Function 30H13:12 channel_mode 11 = 25khz channel mode 00 = 12.5khz channel mode 10,01=reserved 30H6 tx_on 1 = on 0 = off 30H5 rx_on 1 = on 0 = off 5. Deep sleep Bit Name Function 3

28、0H2 pdn_reg The same as pdn pin 1 = enable 0 = disable While Normal mode, pdn_reg and PDN pin must be high at the same time. Only one of pdn_reg and PDN pin is low ,which can turn into deep sleep. 6. TX voice channel Bit Name Function 3cH15:14 voice_sel =00; Tx voice signal from MIC =01; Tx inner si

29、ne tone setted by tone2 =10; Tx code from GPIO1 code_in (gpio1 must be set to 01) =11; not Tx any signal RDA1846 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. 11 7.

30、 TX Pa_bias output voltage RDA1846 Pa_bias pin output voltage can be controlled by 0aH 5:0. Bit Name Function 0aH 5:0 pabias_voltage 000000: 1.01V 000001:1.05V 000010:1.09V 000100: 1.18V 001000: 1.34V 010000: 1.68V 100000: 2.45V 1111111:3.13V 8. Subaudio Bit Name Function 45H2:0 c_mode Ctcss/cdcss m

31、ode sel x00=disable, 001=inner ctcss en, 010= inner cdcss en 101= outter ctcss en, 110=outter cdcss en others =disable 45H3 ctcss_sel 1 = ctcss_cmp/cdcss_cmp out via gpio 0 = ctcss/cdcss sdo out vio gpio 45H4 cdcss_sel 24/23 bit cdcss code sel for both txon and rxon 1 = 24 bit code 0 = 23 bit code 4

32、5H7 neg_det_en If 1,cdcss inverse code will be detected at the same time. 45H11 Pos_det_en If 1, cdcss code will be detected. 45H10 css_det_en If 1, sq detection will add ctcss/cdcss detect result, then 1846 control 1846 voice output on or off. 4aH15:0 ctcss_freq Ctcss/cdcss frequency setting Ctcss

33、freq = ctcss_freq*216 khz It must be set to 134.4Hz when use standard cdcss mode When use ctcss/cdcss, this register must be set both RDA1846 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. 12 in rx and t