dj175_SM.pdf
《dj175_SM.pdf》由会员分享,可在线阅读,更多相关《dj175_SM.pdf(28页珍藏版)》请在收音机爱好者资料库上搜索。
1、 Specifications Circuit Description Parts List Exploded View PC Board View Adjustment Schematic Diagram Block Diagram ALINCO, INC. Service Manual Service Manual DJ-175 SPECIFICATIONS DJ-175 T: E: TFH: TX 144 147.995MHz RX 136 173.995MHz TX 144 145.995MHz RX 144 145.995MHz TX 136 173.995MHz RX 136 17
2、3.995MHz *144 147.995MHz *144 147.995MHz *144 145.995MHz *144 145.995MHz *150 173.995MHz *150 173.995MHz Frequency range: Modulation: Channel steps: Memory channels: Antenna impedance: Frequency stability: Microphone impedance: Power supply: Current drain (Approx.): Temperature range: Ground: Dimens
3、ion: Weight: DTMF: Subaudible Tone (CTCSS): Digital Code SQ. (DCS): * Guaranteed range per specifications F3E (FM), F2D* *T/E models only 5, 10, 12.5, 20, 25 one amplifier (pins 12, 13, and 14) is composed of pre-emphasis and IDC circuits and the other (pins 5, 6, 7, 8, 9, and 10) is composed of a s
4、platter filter. The maximum frequency deviation is obtained by IC105 and input to the cathode of the varicap of the VCO, to change the electric capacity in the oscillation circuit. This produces the frequency modulation. 2. Power Amplifier Circuit The transmitted signal is oscillated by the VCO, amp
5、lified by the pre-drive amplifier (Q101) and drive amplifier (Q106), and input to the final amplifier (Q105). The signal is then amplified by the final amplifier (Q105) and led to the antenna switch (D101) and low-pass filter (L104, L102, L101, C119, C118, C117, C127, C126, C125, C124, C108, and C10
6、1), where un-wanted high harmonic waves are reduced as needed, and the resulting signal is supplied to the antenna. 3. APC Circuit Part of the transmission power from the low-pass filter is detected by D108, converted to DC, and then amplified by a amplifier (IC101). The output voltage controls the
7、bias voltage from the source of Q105 and Q106 to maintain the transmission power constant. 3) PLL Synthesizer System 1. PLL The dividing ratio is obtained by sending data from the CPU (IC113) to pin 10 and sending clock pulse to pin 9 of the PLL IC ( IC101 ). The oscillated signal from the VCO is am
8、plified by the buffer (Q116) and input to pin 8 of IC102. Each programmable divider in IC102 divides the frequency of the input signal by N according to the frequency data, to generate a comparison frequency of 5 or 6.25kHz. 2. Reference Frequency Circuit The reference frequency appropriate for the
9、channel steps is obtained by dividing the 21.25MHz reference oscillation (X102) by 4250 or 3400, according to the data from the CPU (IC113). When the resulting frequency is 5kHz, channel steps of 5, 10, 15, 20, and 30kHz are used. When it is 6.25kHz, channel steps of 12.5, 25 , and 50kHz are used. 3
10、. Phase Comparator Circuit The PLL (IC102) uses the reference frequency, 5 or 6.25kHz. The phase comparator in the IC102 compares the phase of the frequency from the VCO with that of the comparison frequency, 5 or 6.25kHz, which is obtained by the internal divider in IC102. 4. PLL Loop Filter Circui
11、t If a phase difference is found in the phase comparison between the reference frequency and VCO output frequency, the charge pump output (pin 5) of IC102 generates a pulse signal, which is converted to DC voltage by the PLL loop filter and input to the varicap of the VCO unit for oscillation freque
12、ncy control. 5. VCO Circuit A Colpitts oscillation circuit driven by Q108 directly oscillates the desires frequency. The frequency control voltage determined in the CPU (IC113) and PLL circuit is input to the varicaps (D105 and D107). This change the oscillation frequency, which is amplified by the
13、VCO buffer (Q113) and output from the VCO unit. 4) CPU and Peripheral Circuits 1. LCD Display Circuit The CPU turns ON the LCD via segment and common terminals with 1/4 the duty and 1/3 the bias, at the frame frequency is 112.5Hz. 2. Display Lamp Circuit When the LAMP key is pressed, “L” is output f
14、orm pin 67 of CPU ( IC113) to the bases of Q140. Q140 then turn ON and the LEDs (D128 and D129) light. 3. Reset and Backup When the power form the DC jack or external battery increases from Circuits 0V to 2.5 or more, “ H “ level reset signal is output form the reset IC (IC108) to pin 6 of the CPU (
15、IC113), causing the CPU to reset. The reset signal, however, waits at 100, and does not enter the CPU until the CPU clock (X104) has stabilized. 4. S (Signal) Meter Circuit The DC potential of pin 12 of IC103 is input to pin 83 of the CPU (IC113), converted from an analog to a digital signal, and di
16、splayed as the S-meter signal on the LCD. 5. DTMF Encoder The CPU (IC113) is equipped with an internal DTMF encoder. The DTMF signal is output from pin 71, through IC112 (Low-pass filter), and then through the microphone amplifier (IC110), and is sent to the varicap of the VCO for modulation. At the
17、 same time, the monitoring tone passes through the AF circuit and is output form the speaker. 6. TONE Encoder The CPU (IC113) is equipped with an internal tone encoder. The tone signal (67.0 to 250.3Hz ) is output from pin 70 of the CPU to the 21.25MHz reference oscillation (X102) of the PLL referen
18、ce oscillator. 7. DCS Encoder The CPU (IC113) is equipped with an internal DCS code encoder. The code (023 to 754) is output from pin 70 of the CPU to the 21.25MHz reference oscillation (X102) of the PLL reference oscillator. 8. CTCSS, DCS Decoder The voice band of the AF output signal from pin 9 of
19、 IC103 is cut by sharp active filter IC111 and amplified, then led to pin 80 of CPU. The input signal is compared with the programmed tone frequency code in the CPU. The squelch will open when they match. 9. Clock Shift In the unlikely event that CPU clock noise is present on a particular operating
20、frequency programmed into the radio, you can shift the CPU clock frequency to avoid the CPU clock-noise. The output signal from pin 8 of the CPU turns on Q127. Then the oscillation frequency of X104 will be shifted about 200 ppm. Ref. No.Parts No.Parts nameVersionRef. No.Parts No.Parts name C101CU35
21、35GRM36B102K50PTC173 C102CU3535GRM36B102K50PTC174 C103CU3519GRM36CH470J50PTC175 C104CU3535GRM36B102K50PTC176CU3502GRM36CK010C50PT C105C177CU3535GRM36B102K50PT C108CU3535GRM36B102K50PTC178CU3513GRM36CH150J50PT C109CU3512GRM36CH120J50PTC179CU3535GRM36B102K50PT C110CU3505GRM36CH040C50PTC180CU3515GRM36C
22、H220J50PT C111CU3535GRM36B102K50PTC181CU0119GRM21BB30J106KE18L C112CU3520GRM1552C1H560JD01DC182CU3554GRM36B104K10PT C113CU3535GRM36B102K50PTC183CU3535GRM36B102K50PT C114CU3503GRM36CK020C50PTC184CU3547GRM36B103K16PT C115C185CU3535GRM36B102K50PT C116CU3512GRM36CH120J50PTC186 C117CU3513GRM36CH150J50PTC
23、187CU3513GRM36CH150J50PT C118CU3513GRM36CH150J50PTC188CU35081005 CH 50V 7PF D C119CU3513GRM36CH150J50PTC189CU3535GRM36B102K50PT C120C190 C122CU3559GRM155B30J105KE18DC191CU3137GRM188B31C105KA92D C123C192CU3535GRM36B102K50PT C124CU3512GRM36CH120J50PTC193CU3514GRM36CH180J50PT C125CU3512GRM36CH120J50PTC
24、194CU3554GRM36B104K10PT C126CU3513GRM36CH150J50PTC195CU3535GRM36B102K50PT C127CU3514GRM36CH180J50PTC196CU3502GRM36CK010C50PT C129CU3512GRM36CH120J50PTC197CU3527GRM1552C1E221JD01D C130CU3514GRM36CH180J50PTT, E, EUKC198CU3554GRM36B104K10PT C131CU3517GRM36CH330J50PTC199CU3515GRM36CH220J50PT C132CU3516G
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- dj175_SM
收音机爱好者资料库所有资源均是用户自行上传分享,仅供网友学习交流,未经上传用户书面授权,请勿作他用。



Marshall-9100-62-02-Schematic电路原理图.pdf


