djs40T_SM.pdf
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1、DJ-S40T / E Service Manual CONTENTS SPECIFICATIONS 1) GENERAL . 2 2) TRANSMITTER . 2 3) RECEIVER . 2 CIRCUIT DESCRIPTION 1) Receiver system . 3 2) Terminalmitter system . 4 3) PLL, VCO Circuit. 4 4) M38224M6M . 5 SEMICONDUCTOR DATA 1) M64082A (XA0543) . 7 2) NMJ2070MT1 (XA210) . 8 3) NJM2904V (XA057
2、3). 8 4) NJM2902V-TE1 (XA0596) . 9 5) TA31136FN (XA0404). 9 6) UPC2771T (XA0545). 10 7) CAT24WC16JITE13 (XA0855). 10 8) S-816A30AMC (XA0848). 10 9) S-80827ALNP (XA0857). 11 10) MRF9745T1 (XE0034). 11 11) Transistor, Diode and LED Outline Drawings. 12 12) LCD Connection . 13 EXPLODED VIEW 1) Front Vi
3、ew. 14 2) Bottom View. 15 PARTS LIST MAIN Unit . 1620 SW Unit . 20 Mechanical Parts . 20 Packing. 20 ADJUSTMENT. 2122 PC BOARD VIEW 1) UP0433(1/2) side A . 23 2) UP0433(1/2) side B . 24 3) PTT Unit WIRING . 25 SCHEMATIC DIAGRAM. 26 BLOCK DIAGRAM. 27 ALINCO,INC. 2 SPECIFICATIONS 1) GENERAL Frequency
4、coverageT : TX 430 449.995MHz RX 410 470MHz E : TX 430 439.995MHz RX 430 439.995MHz TA : TX 410 470MHz RX 410 470MHz ModeF3E (FM) Channel steps5, 10, 12.5, 15, 20, 25, 30 & 50kHz Memory channels99 channels+1 CALL channel Antenna connectorSMA (50 unbalanced) Frequency stability5 ppm Microphone impeda
5、nce2k nominal Power supply4.5 16.0V DC (EXT.termonai) 3.6 16.0V DC (BATT terminal) Current600mA (typical) Transmit high at 1W 150mA (typical) Receive at 280mW 40mA (typical) standby 15mA (typical) Battery save on Usable temperature range-10 +60 C (14 140F) Dimensions56 (W) 102 (H) 30 (D) mm (with ED
6、H-31) 2.2(W) 4.0(H) 1.18(D) inches (with EDH-31) (Projections not included) WeightApprox. 160g (5.6oz) (with EBP-53N) Approx. 95g (3.3oz) (without Battery) Sub audible Tone(CTCSS) encoder/decoder installed (38tones) 2) TRANSMITTER Output powerApprox. 1.0W EBP-53N installed Approx. 1.0W 13.8V DC Appr
7、ox. 0.6W EDH-31 installed Approx. 0.2W (LOW) Modulation systemVariable reactance frequency modulation Spurious emissions-60dB or less Max. frequency deviation5kHz 3) RECEIVER Receive systemDouble conversion superheterodyne Intermediate frequencies1st 21.7MHz / 2nd 450kHz Sensitivity(12dB SINAD)-14.0
8、dB (0.2uV) or less 430 450MHz Selectivity-6dB : 12kHz or more -60dB : 28kHz or less Audio output power280mW or higher( 8 load) 200mW (810% THD) 3 CIRCUIT DESCRIPTION 1) Receiver System The receiver system is a double superheterodyne system with a 21.7MHz first IF and a 450kHz second IF. 1. Front End
9、 The signal from the anntena is pssed through low-pass filter and input to RF coil L24 and L17(band pass filter). The signal from L24 and L17 is amplified by Q9,Q10 and led to the band pass filter, and let to the first mixer base of Q11. 2. First Mixer The amplified signal (f0) by Q9,Q10 is mixed ei
10、th the first local oscillator signal(f0-21.7MHz) from the PLL circuit by the first stage mixer Q11 and so is converted into the first IF signal. The unwanted frequency band of the first IF signal is eliminated by the monolithic crystal filter FL3,and led to IF amplifier Q8. 3. IF Circuit The first I
11、F signal is amplified by Q8, and input to pin 16 of IC3, where it is mixed withthe second local oscillator signal(21.25MHz)and so is converted into the second IF signal(450kHz). The second IF signal is output from pin3 of IC3, and unwanted frequency band of second IF signal is eliminated by a cerami
12、c filter FL2. The resulting signal is then amplified by the second IF limiting amplifier, and detected by quadrature circuit. the audio signal is output from pin9 of IC3 4.Audio Circuit The demodulated signal in IF IC3 contains the audio signal and CTCSS signal . CTCSS signal is passed through the l
13、ow-pass filter of IC5 and led to TIN port of CPU to be decoded. The audio signal is input to the main volume VR3 passing through de-emphasis circuit and high-pass filter circuit of Q19.The signal of which level is adjusted at the main volume VR3 is input to IC6 of AF amp, then it is amplified to the
14、 level that can drive the speaker. 5.Squelch Circuit The noise in the audio signal from IC3 is passed through the noise-filter and input to pin8 of IC3. IC3 includes filter amplifier,high-pass filter and rectifier. The rectified voltage level from pin14 of IC3 is deliverd to the comparator of the CP
15、U. The voltage is led to pin1 of CPU and compared with the setting voltage.The squelch will open if the input voltage is lower than the setting voltage. During open squelch ,pin11(AFS)of CPU becomes”H”level and pin9(AFP)of CPU becomes”L”level, AF control signal is being controlled and sounds is outp
16、utted from the speaker. 4 2)Transmitter System 1.Microphone Amplifier The input signal from built-in or external microphone is led to the microphone mute circuit Q15,pre-emphasis circuit ,IDC circuit IC4,the signal is input to the maximum deviation adjustment volume VR2.Then mixed at the add VR2 wit
17、h the CTCSS tone signal which is generated by CPU,Then it is input to VCO as the modulation signal. 2.Power Amplifier The signal from VCO is amplified by IC1 and then passed through the low-pass filter, the antenna switch circuit and the output low-pass filter. The unwanted harmonics frequency signa
18、l is eliminated by the low-pass filter and input to the antenna. 3)PLL,VCO Circuit Output frequency of PLL circuit is set by the serial data from microprocessor. PLL circuit consists of VCO Q2,buffer amplifier Q6. The pulse wave output of chage pump is converted to DC voltage by PLL loop filter circ
19、uit,snd supplied to D2,D15 of varicap diode in VCO unit. The frequency modulation is executed when audio signal voltage is supplied to the varicap D3. When PLL is unlocked,pin10 of IC2 goes to “High”. 5 4) M38224M6M CPU Terminal Connection (TOP VIEW) 6 Terminal function of CPU No. Pin Name FunctionI
20、/OLogicDescriptionNo. Pin Name FunctionI/OLogicDescription 1P67SQLIA/DNoise level input for squelch 2P66KEYIA/DKey input (,V/M) 3P65VOXOActiv highPower cont. 4P64EXTDCIA/DExt voltage input 5P63BP1IA/DBand plan 1 6P62TINIA/DCTCSS tone input 7P61SMTIA/DS-meter input 8P60BATTIA/DBatt voltage input 9P57
21、AFPOActiv lowAudio Amp ON/OFF 10P56BEEPI/O PulseBeep sound out 11P55AFSOActiv highAudio signal ON/OFF 12CNTR0TBSTI/O PulseArt tone output 13P53BP3IBand plan 3 14P52MONIIActiv lowMonitor key input 15P51PSWIActiv lowPower switch input 16P50STBOPulseStrobe for PLL 17P47DATAI/O PulseData for PLL 18P46CL
22、KOPulseClock for PLL 19TxDCTXOPulseUART data transmission output 20RxDCRXIPulseUART data reception input 21P43SCRIActiv highAlarm signal input 22INTOBUIActiv lowBack up signal detection input 23P41PTTKIActiv highPTT signal input 24P40BP4IActiv highBand plan 4 25RESETRESETIActiv lowReset input 26P71S
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