dr135_435MK2_SM.pdf

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1、DR-135 / DR-435MkII Service Manual CONTENTS SPECIFICATIONS General. 2 Transmitter . 2 Receiver . 2 CIRCUIT DESCRIPTION 1) Receiver System DR-135 . 3, 4 2) Transmitter System DR-135 . 5 3) PLL Synthesizer Circuit DR-135 . 5, 6 4) Receiver System DR-435 . 6, 7 5) Transmitter System DR-435 . 8 6) PLL S

2、ynthesizer Circuit DR-435 . 8, 9 7) CPU and Peripheral Circuit . 9, 10 8) Power Supply Circuit. 10 9) M38267M8L272GP (XA0851). 1113 SEMICONDUCTOR DATA 1) M5218AFP (XA0068). 14 2) NJM7808FA (XA0102) . 14 3) TC4S66F (XA0115) . 14 4) BU4052BF (XA0236) . 15 5) TA75S01F (XA0332) . 15 6) TC4W53FU (XA0348)

3、. 15 7) TA31136FN (XA0404). 16 8) LA4425A (XA0410). 16 9) M67746 (XA0412) . 17 10) M57788M (XA0077A) . 18 11) NJM2902V (XA0596). 19 12) 24LC32AT (XA0604) . 19 13) S-80845ALMP (XA0620) . 19 14) TK10931V (XA0666). 20, 21 15) L88MS05TLL (XA0675) . 22 16) M64076AGP (XA0915) . 23 17) Transistor, Diode an

4、d LED Outline Drawing . 24 18) LCD Connection (TTR3626UPFDHN) . 25 EXPLODED VIEW 1) Top and Front View . 26 2) Bottom View. 27 3) LCD Assembly. 28 PARTS LIST CPU Unit . 29, 30 MAIN Unit DR-135 . 3033 MAIN Unit DR-435 . 3336 VCO Unit DR-435 . 36 Mechanical Parts . 36, 37 Packing Parts. 37 ACCESSORIES

5、. 37 ACCESSORIES (SCREW SET). 37 TNC (EJ41U) . 38 TNC (EJ41U) Packing Parts . 39 DR-135 ADJUSTMENT 1) Adjustment Spot . 40 2) VCO and RX Adjustment Specification . 41 3) Tx Adjustment Specification. 41 4) Rx Test Specification. 42 5) Tx Test Specification . 43 DR-435 ADJUSTMENT 1) Adjustment Spot .

6、44 2) VCO and RX Adjustment Specification . 45 3) Tx Adjustment Specification. 46 4) Rx Test Specification. 47 5) Tx Test Specification . 48 PC BOARD VIEW 1) CPU Unit Side A . 49 2) CPU Unit Side B . 49 3) MAIN Unit Side A DR-135 (UP0467A) . 50 4) MAIN Unit Side B DR-135 (UP0467A) . 50 5) MAIN Unit

7、Side A DR-435 (UP0468A) . 51 6) MAIN Unit Side B DR-435 (UP0468A) . 51 7) TNC Unit Side A (UP0402) (option) . 52 8) TNC Unit Side B (UP0402) (option) . 52 SCHEMATIC DIAGRAM 1) CPU Unit DR-135 / DR-435 . 53 2) MAIN Unit DR-135 . 54 3) MAIN Unit DR-435 . 55 4) TNC Unit (option). 56 BLOCK DIAGRAM 1) DR

8、-135 . 57 2) DR-435 . 58 ALINCO,INC. 2 Frequency coverage DR-135 DR-435 T Mk 118.000 135.995MHz (AM RX) 136.000 173.995MHz (RX) 144.000 147.995MHz (TX) 350.000 511.995MHz (RX) 430.000 449.995MHz (TX) E Mk 144.000 145.995MHz (RX,TX) Operating mode FM16K0F3E (Wide mode)8K50F3E (Narrow mode) Frequency

9、resolution 5, 8.33, 10, 12.5, 15, 20, 25, 30, 50 kHz Number of memory Channels 100 Antenna impedance 50 unbalanced Power requirement 13.8V DC 15% (11.7 15.8V) Ground method Negative ground Current drain Receive 0.6A (max.) 0.4A (Squelched) Transmit 11.0 A max. 10.0 A max Operating temperature -10C 6

10、0C Frequency stability 2.5 ppm Dimensions 142 (w)40 (h)174 (d) mm (14240188mm for projection included) Weight Approx. 1.0Kg Output power Hi 50W 35W Mid 10W 10W Low Approx. 4W Approx. 5W Modulation system Variable reactance frequency modulation Maximum Frequency deviation 5kHz (Wide mode) 2.5kHz (Nar

11、row mode) Spurious emission -60dB Adjacent channel power -60dB Noise and hum ratio -40dB (Wide mode) -34dB (Narrow mode) Microphone impedance 2k Sensitivity -16dBu for 12dB SINAD Receiver circuit Double conversion super-heterodyne Intermediate frequency 1st 21.7MHz 2nd 450kHz 1st 30.85MHz 2nd 455kHz

12、 Squelch sensitivity -18dBu Adjacent channel selectivity -65dB (Wide mode) -55dB (Narrow mode) Inter-modulation rejection ratio 60dB Spurious and image rejection ratio 70dB Audio output power 2.0W (8, 10 % THD) ! NOTE : All specifications are subject to change without notice or obligation. SPECIFICA

13、TIONS General Transmitter Receiver 3 CIRCUIT DESCRIPTION 1) Receiver System DR-135 The receiver system is a double super-heterodyne system with a 21.7MHz first IF and a 450kHz second IF. 1. Front End The received signal at any frequency in the 136.000MHz to 173.995MHz range is passed through the low

14、-pass filter (L116, L115, L114, L113, C204, C203, C202, C216 and C215) and tuning circuit (L105, L104 and D105, D104), and amplified by the RF amplifier (Q107). The signal from Q107 is then passed through the tuning circuit (L103, L102, and variable capacitor D103, D102) and converted into 21.7MHz b

15、y the mixer (Q106). The tuning circuit, which consists of L105, L104, variable capacitor D105 and D104, L103, L102, variable capacitor D103 and D102, is controlled by the tracking voltage from the VCO. The local signal from the VCO is passed through the buffer (Q145), and supplied to the source of t

16、he mixer (Q106). The radio uses the lower side of the super- heterodyne system. 2. IF Circuit The mixer mixes the received signal with the local signal to obtain the sum of and difference between them. The crystal filter (XF102, XF101) selects 21.7 MHz frequency from the results and eliminates the s

17、ignal of the unwanted frequencies. The first IF amplifier (Q105) then amplifies the signal of the selected frequency. 3. Demodulator Circuit After the signal is amplified by the first IF amplifier (Q105), it is input to pin24 of the demodulator IC (IC108). The second local signal of 21.25MHz (shared

18、 with PLL IC reference oscillation), which is oscillated the external oscillator X102 (VCTCXO), is input through pin 1 of IC108. Then, these two signals are mixed by the internal mixer in IC108 and the result is converted into the second IF signal with a frequency of 450kHz. The second IF signal is

19、output from pin 3 of IC108 to the ceramic filter (FL102 or FL101), where the unwanted frequency band of that signal is eliminated, and the resulting signal is sent back to the IC108 through pin 5. The second IF signal input via pin 5 is demodulated by the internal limiter amplifier and quadrature de

20、tection circuit in IC 108, and output as an audio signal through pin 12. 4 4. Audio Circuit The audio signal from pin 12 of IC 108 is amplified by the audio amplifier (IC104:A, IC120), and switched by the signal switch IC (IC111) and then input it to the de-emphasis circuit. And is compensated to th

21、e audio frequency characteristics in the de-emphasis circuit (R203, R207, R213, R209, C191, C218, C217) and amplified by the AF amplifier (IC104:D). The signal is then input to volume (VR1). The adjusted signal is sent to the audio power amplifier (IC117) through the pin 1 to drive the speaker. 5. S

22、quelch Circuit The detected output which is outputted from pin 12 of IC108 is inputted to pin 19 of IC108 after it was been amplified IC104:A, IC120 and it is outputted from pin 20 after the noise component was been eliminated from the composed band pass filter in the built in amplifier of the IC, t

23、hen the signal is rectified by the internal diode in IC108 to convert into DC component. The adjusted voltage level at VR101 is delivered to the comparator of the CPU.The voltage is led to pin 2 of CPU and compared with the setting voltage. The squelch will open if the input voltage is lower than th

24、e setting voltage. During open squelch, pin 30 (SQC) of the CPU becomes L level, AF control signal is begin controlled and sounds is outputted from speaker. 6. AIR Band Reception (T only) When the frequency is within 118.000 135.995MHz, Q110 automatically turns on, pin 14 of IC 108 becomes H level a

25、nd the condition becomes in AM detection mode. The receiver signal passed through the duplexer is let to the antenna switch (D107, D101). After passing through the band-pass filter, the signal is amplified by RF amplifier Q112. Secondly the signal is mixed with the signal from the first local oscill

26、ator in the first-mixer Q106, then converted into the first IF. Its unwanted signal is let to pin 24 of IC106. Then converted into the second IF. And is demodulated by AM decoder of IC106, and is output from pin 13 as the AF signal. 7. WIDE/NARROW Switching Circuit The second IF 450kHz signal which

27、passes through filter FL101 (wide) and FL102 (narrow) during narrow, changes its width using the width control switching IC103 and IC102. 5 2) Transmitter System DR-135 1. Modulator Circuit The audio signal is converted to an electrical signal by the microphone, and input it to the microphone amplif

28、ier (Q6). Amplified signal which passes through mic-mute control IC109 is adjusted to an appropriate mic-volume by means of mic-gain adjust VR106. IC114:A and B consists of two operational amplifiers; one amplifier (pin 1, 2 and 3) is composed of pre-emphasis and IDC circuit and the other (pin 5, 6

29、and 7) is composed of a splatter filter. The maximum frequency deviation is obtained by VR107. And input to the signal switch (IC113) (9600 bps packet signal input switch) and input to the cathode of the variable capacitor of the VCO, to change the electric capacity in the oscillation circuit. This

30、produces the frequency modulation. 2. Power Amplifier Circuit The transmitted signal is oscillated by the VCO, amplified by the drive amplifier (Q145) and younger amplifier (Q115, Q144), and input to the final power module (IC110). The signal is then amplified by the final power module (IC110) and l

31、ed to the antenna switch (D110) and low-pass filter (L113, L114, L115, L116, C215, C216, C202, C203 and C204), where unwanted high harmonic waves are reduced as needed, and the resulting signal is supplied to the antenna. 3. APC Circuit Part of the transmission power from the low-pass filter is dete

32、cted by D111 and D112, converted to DC. The detection voltage is passed through the APC circuit (Q118, Q117, Q116), then it controls the APC voltage supplied to the younger amplifier Q115 and the final power module IC110 to fix the transmission power. 3) PLL Synthesizer Circuit DR-135 1. PLL The div

33、iding ratio is obtained by sending data from CPU (IC1) to pin 2 and sending clock pulses to pin 3 of the PLL IC (IC116). The oscillated signal from the VCO is amplified by the buffer (Q134 and Q135) and input to pin 15 of IC116. Each programmable divider in IC116 divides the frequency of the input s

34、ignal by N according to the frequency data, to generate a comparison frequency of 5 or 6.25 kHz. 2. Reference Frequency Circuit The reference frequency appropriate for the channel steps is obtained by dividing the 21.25 MHz reference oscillation (X102) by 4250 or 3400, according to the data from the

35、 CPU (IC1). When the resulting frequency is 5 kHz, channel step of 5, 10, 15, 20, 25, 30 and 50 kHz are used. When it is 6.25 kHz, the 12.5 kHz channel step is used. 6 3. Phase Comparator Circuit The PLL (IC116) uses the reference frequency, 5 or 6.25 kHz. The phase comparator in the IC116 compares

36、the phase of the frequency from the VCO with that of the comparison frequency, 5 or 6.25 kHz, which is obtained by the internal divider in IC116. 4. PLL Loop Filter Circuit If a phase difference is found in the phase comparison between the reference frequency and the VCO output frequency, the charge

37、 pump output (pin 13) of IC116 generates a pulse signal, which is converted DC voltage by the PLL loop filter and input to the input to the variable capacitor of the VCO unit for oscillation frequency control. 5. VCO Circuit A Colpitts oscillation circuit driven by Q131 directly oscillates the desir

38、ed frequency. The frequency control voltage determine in the CPU (IC1) and PLL circuit is input to the variable capacitor (D122 and D123). This change the oscillation frequency, which is amplified by the VCO buffer (Q134) and output from the VCO area. 6. VCO Shift Circuit During transmission or the

39、AIR band Reception (118 136 MHz), the VCO shift circuit turns ON Q138, change control the capacitance of L123 and safely oscillates the VCO by means of H signal from pin 16 of IC116. 4) Receiver System DR-435 The receiver system is a double super-heterodyne system with a 30.85MHz first IF and a 455k

40、Hz second IF. 1. Front End The received signal at any frequency in the 430.000MHz to 449.995MHz range is passed through the low-pass filter ( L115, L114, L116, C204, C203, C202, C216 and C215) and amplified by the RF amplifier (Q107). The signal from Q107 is then passed through the BPF circuit (L103, L102) and converted into 30.85MHz by the mixer (Q106). The local signal from the VCO is passed through the buffer (Q503, Q504), and supplied to the