TR-7400A_serv.pdf
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1、 Your KENWOOD Model TR-7400A is a high-quality 2-meter transceiver for use in ama- teur radio mobile stations as well as base stations . It contains a PLL frequency syn- thesizer developed and engineered through KENWOODs elaborate VHF technology to provide high performance and outstanding technical
2、characteristics . The TR-7400A is capable of transmitting or receiving F3 FM signals on up to 800 Chan- nels at intervals of 5 kHz. having 25W RF output power . CONTENTS SPECIFICATIONS . 3 FINAL TRANSISTOR SPECIFICATIONS . 4 BLOCK DIAGRAM . 5 CIRCUIT DESCRIPTION . 6 PARTS ALIGNMENT . 11 PC BOARD PA
3、UNIT (X45-1090-10) . 13 PD UNIT (X50-1380-10) . 14 VCO UNIT (X50.1370.10) . 15 INDICATOR UNIT (X54-1210-10) . 16 RX UNIT (X55-1150-10) . 17 TX UNIT (X56-1230-10) . 18 PARTS LIST . 19 PACKING . 25 DISASSENIBLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TROUBLES
4、HOOTING . 29 LEVEL DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ADJUSTNIEIUTS . 33 SCHEMATIC DIAGRAM . 40 SPECIFICATIONS GENERAL Semiconductors Frequency Range Frequency Synthesizer Synthesizer Stability Mode Number of Channel Operating Temperature Power
5、 Voltage Grounding Antenna lmpedance DC Current Dimension Weight Transistors 58 FETs 8 I C s 19 Diodes 63 144.00 to 147.995 MHz Digital (TTL Logic) control of phase locked VCO Less than k750 Hz at 2 5 FM 800 -20 to +50c 11.5 VDC to 16.0 VDC (13.8 VDC as reference) Negative grounding 50 52 Less than
6、1A in receive with no input signal Less than 8A in transmit (HI) Less than 4.5A in transmit (LOW) (at 13.8 VDC) 182 mm (7-3116) wide 74 mm (2-718) high 270 mm (10-518) deep Approx. 2.8 kg (6.2 Ibs.) TRANSMIT SECTION RF Output Power High 25 watts (min.) Low approx. 5 watts (adjustable up to 15 watts)
7、 Modulation Variable reactance direct shift Max. Frequency Deviation k5 kHz Spurious Radiation Less than -60 dB Touch Tone Input Impedance 600 52 Microphone Dynamic microphone with PTT switch, 500 52 RECEIVE SECTION Circuitry Intermediate Frequency Squelch Sensitivity Pass Band Width Selectivity (2
8、Signal) Image Rejection Spurious Interference lntermodulation Audio Output OPTION i) Tone Squelch Tone Deviation Encorder Response Frequency Stability Tone Squelch Open Sensitivity Tone Distortion ii) Tone Burst Burst Time Double superheterodyne 1st IF 10.7 MHz 2nd IF 455 kHz Less than 0.4 pV for 20
9、 dB quieting (Less than 1 ,uV for 30 dB SIN) Less than 0.25 ,uV More than 12 kHz at 6 dB down More than 72 dB at 30 kHz of adjacent channel More than 70 dB More than 60 dB More than 66 dB More than 1.5 watts across 8 52 load (10% distortion) k0.5 kHz (adjusted) Less than 0.5 sec. Less than 21% Less
10、than SlNAD 10 dB Less than 5% Approx. 0.5 sec. (adjusted) NOTE: The circuit and ratings may change without notice due to development in technology. Final Transistor (2N6083) Specifications Maximum Ratings TA = 2 5 O (Unless otherwise specified) Characteristics Standard TA = 25OC (Unless otherwise sp
11、ecified.) Item Unit Ratings V cso V 36 Symbol VCEO V 18 LTPD level Condition 5 5 FE Cob VEBO V 4 Minimum 1 1 VCE = 5V, IC = 1A 5 5 1 / VCB = 15V, f =0.1 MHz 1 Standard value Maximum 5 Vcc = 12.5 V, POUT =30W ) 5.7 dB 10 1 f = 175 MHz, Vcc = 12.5 V, POUT =30W rl 1 6 5 % 10 1 f = 175 MHz, ICES VCE= 15
12、 V, TC = 55OC 10 mA 5 1 I c A 4 Unit VCB = 15 V ICBO 1 - r n A BVCES Ic = 15 mA V PD T A = c W 6 5 BVCEO BVEBO - Stud torque inIb 6.5 Ic = 100 mA V - Tstg c -65 to 200 - IE = 5 mA 4 , V BLOCK DIAGRA! RX UNlT (X55-1150-10) r- - - - - I I I I L ,-,-,-, + - - - To 0 1 3 (OFF circuit of VCO output) 0 4
13、5 v UNLOCK Fig. 3 PHASE DETECTOR Block Diagram Indicator PROGRAMMABLE COUNTER AND TX-OFFSET ing counter which counts in the order of 0, 4, 3, 2, 1, 0 CIRCUITS (5), 4, 3, . receiving input pulses, assuming that preset These circuits, consisting of IC5 to IC12, are basically a MODULO-N PROGRAMMABLE co
14、unter of IC5 to IC7 added with an EXTENDER consisting of a D-flip-flop of lClO and a logic circuit of IC8, 9, I I and 12. It belongs to the high-speed scaling method. Fig. 4 shows the opera- tion of the circuits. The operation is simply described below. A division ratio is preset in the MC74416 of I
15、C5 to IC7 with a BCD code. The division ratio preset lies be- tween 400 and 799 in relation to digital indication (144.00 - 147.99). While, since the IF signal entering the MC 74416 is 5.37 - 9.36 MHz to eliminate beat interference in reception, the division ratio must be 537 - 936 actually. For thi
16、s purpose the gate, No, serves to raise the division ratio by 137. The gate circuit, U and D, shifts frequency by f600 kHz for repeater operation which is equivalent to the divsion ratio of 137 f 60. MC74416 is a decrement- value is 5 and PE is 0 (L level). But output becomes 1 (H level) only when t
17、he count is 0. It means that five input pulses make one out- put pulse and the frequency is divided to 115. With three ICs connected in cascade, the division ratio can be raised up to 999. IClO is a high speed D-flip-flop which improves the operating frequency of MC74416, 8 MHz (min.), by a factor o
18、f two or more with the aid of gates A and B. Fig. 4 shows the case where the least significant digit of the actual division ratio, Ns, is 7. Although resetting should be done at the rise of input pulse and presetting should be done at the decay of the input pulse when the count has become three, the
19、 level at A is set to L at the count of five and it becomes the output of IC10-1 at the next pulse. This output (01) resets the MC74416 and presets it to N at the same time, but counting is not per- formed since PE remains at the L level during the next Fig. 4 Block Diagram of PROGRAMMABLE COUNTER a
20、nd TX-OFFSET Circuit CIRCUIT DESCRIPTIONS input pulse and it is reset. The operating frequency has been improved because resetting and presetting are done in one cycle of input pulse but not in half a cycle, and the delay time, t2, of the high speed D-flip-flop in lClO is much smaller than the delay
21、 time, t l , from IC5, 6 and 7 and logic circuit to point A. Next, operation is explained in relation to the TX off- set switch setting. 1 +600 During reception, this is the same as in (2). During transmission, SR 1 is turned on and becomes U in Table 2. Gate U therefore opens and gates No and D are
22、 closed. At this setting, Ns = I N + 197 (137 + 60), and it operates as an extender when IC5, IC6 and IC7 take code 8, 0 and 5 respectively, to perform division of N + 197. 2 No (SIMP) (F) and (G) make up No in Table 2. Gates No and U open and gate D IS closed. At this setting, the relation, Ns = N
23、+ 137, holds between preset value N and actual divi- sion ratio Ns. It is enough to decrement the counter after division of N (decrernenting) has completed and perform resetting and presetting just when the count has become 137. For this purpose, IC5, IC6 and IC7 do not take code 8, 6 and 3 respecti
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