Vertex_VXR-9000_UHF_serv.pdf

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1、2003 VERTEX STANDARD CO., LTD. EC044U90A Rack Mount Repeater VXR-9000 (UHF) Service Manual Specifications .A-1 DSUB 15-pin Accessory Connector . B-1 Exploded View all adjustments can be performed from the personal computer, using with the Vertex Standard VPL-1 Programming Cable and CE60 Software. Wh

2、ile we believe the information in this manual to be correct, Vertex Standard assumes no liability for damage that may occur as a result of typographical or other errors that may be present. Your cooperation in pointing out any inconsistencies in the technical information would be appreciated. Conten

3、ts Board Units (Schematics, Layouts the local signal then passes through buffer amplifier Q1059 (2SC5226) and first local amplifier Q1019 (2SC3357) to the first mixer Q1018 (SPM5001). The 73.35 MHz first IF signal is applied to monolithic crys- tal filters XF1001 and XF1002 which strip away unwanted

4、 mixer products, and the IF signal is applied to the first IF amplifiers Q1022 (2SC5226). The amplified first IF sig- nal is then delivered to the FM IF subsystem IC Q1028 (TA31136FN), which contains the second mixer, second local oscillator, limiter amplifier, noise amplifier, and FM detector. The

5、second local oscillator signal, generated by the 72.895 MHz crystal X1002, produces the 455 kHz second IF sig- nal when mixed with the first IF signal within Q1028 (TA31136FN). The second IF signal passes through ceram- ic filter CF1001 or CF1002 which strips away all but the desired signal, and the

6、n passes through the limiter am- plifier within Q1028 (TA31136FN) to ceramic discrimi- nator CD1001, which removes any amplitude variations in the 455 kHz IF signal before detection of speech. The detected audio passes through the low pass filter, consist- ing of R1199 and C1244, which rejects the 4

7、55 kHz IF com- ponent. The audio signal from the MAIN Unit is delivered to the CNTL Unit and passes through the audio amplifier Q1020 (NJM2904V) to the active high pass filter section of Q3020 (FX805LG), which rejects the sub-audible frequency com- ponent. The filtered audio signal is delivered to e

8、lectron- ic volume Q1056, which adjusts the audio sensitivity to compensate for audio level variations, then passes through audio amplifier Q1020 (NJM2904V), audio switch Q1040 (BU4066BCFV), attenuator consisting of R1233, and lim- iter amplifier Q1050 (NJM2904V), to the electronic vol- Circuit Desc

9、ription ume control Q1056 (M51132FP), where the maximum de- viation is set. The audio signal subsequently passes through the 3-section active low pass filter consisting of Q1017-1/-2/-3 (NJM2902V) and audio amplifier Q1001 (NJM2902V) to providing the repeater transmit audio. A portion of the audio s

10、ignal from the active high pass filter section of Q4024 (NJM2902V) is de-emphasized con- sisting of Q3036 (TA75S01F), R3198, and C3144, provid- ing a flat audio response. The filtered audio then passes through the active band pass filter Q3021 (NJM2902V) and audio mute gate Q3015 (DTC323TK) to audio

11、 power amplifier Q1057 (TDA2003), providing up to 2 Watts of audio power to the 8 Ohm loudspeaker. SUB-AUDIBLE SIGNALING (DECODER) A portion of the audio signal from the audio amplifier Q1020 (NJM2904V) passes through the 3-section active low pass filter Q1025 (NJM2902V) and the low pass fil- tering

12、 section of Q3020 (FX805LG) to separate the CTC- SS tones from the received audio signal. The CTCSS tones are sent to the CTCSS decoder section of Q3020 (FX805LG). When a CTCSS tone is received, the CTCSS information is delivered to pin 77 of the Main CPU Q3014 (HD64F2238) from pin 4 and 8 of Q3020

13、(FX805LG) which compares the CTCSS tone with the programmed tone. Another portion of the audio signal passes through the 3- section active low pass filter Q3044 (NJM2902V) to sepa- rate the DCS codes from the received audio signal. The low pass filtered signal passes through the phase detector Q3044

14、 (NJM2902V) to pin 39 of the Main CPU Q3014 (HD64F2238). When a DCS code is received, the Main CPU Q3014 (HD64F2238) compares the DCS code with the programmed code. If the received CTCSS tone or DCS code matches the pro- grammed tone or code, pin 4 of the Main CPU Q3014 (HD64F2238) goes low, turning

15、 off the squelch switch Q3015 (DTC323TK) and passing the received audio sig- nal to the audio power amplifier Q1057 (TDA2003V). SQUELCH CONTROL The squelch circuit consists of noise amplifier Q1033 (2SC4116GR) and noise detector D1015 (MA143) on the MAIN Unit, and control circuitry within Main CPU Q

16、3014 (HD64F2238) on the CNTL Unit. When no carrier is received, noise at the output of the au- dio detector stage of Q1028 (TA31136FN) is amplified by Q1033 (2SC4116GR), and then rectified by D1015 (MA143) to provide a DC control voltage for the squelch switch. The resulting DC voltage is delivered

17、to pin 23 of J1005. The DC voltage from the MAIN Unit is delivered to the A-D analog input port (pin 51) of the Main CPU Q3014 (HD64F2238) on the CNTL Unit, which compares the F-1 squelch threshold level to that which is memorized in EE- PROM Q3006 (BR24L32F) or set by the front panel SQL control. R

18、X PLL AND VCO CIRCUITS The receivers PLL circuitry consists of PLL subsystem IC Q1052 (MB15A02PFV1) on the MAIN Unit, which con- tains a reference oscillator/divider, serial-to-parallel data latch, programmable divider, phase comparator and a swallow counter. Stability is obtained by a regulated 5 V

19、DC supply via Q1062 (L78M05T) and temperature com- pensated 14.4 MHz crystal oscillator X1003. The RX VCO made up two VCO circuit, one is Low-Band RX VCO, consisting of FET Q1048 (2SK508) and varactor diodes D1018 and D1019 (both 1SV282), and another one is High-Band RX VCO, consisting of FET Q1049

20、(2SK508) and varactor diodes D1020 and D1021 (both 1SV282), os- cillates between 376.65 MHz and 416.65 MHz according to the programmed receiving frequency. The RX VCO output passes through buffer amplifier Q1059 (2SC5226) and first local amplifier Q1019 (2SC3357) to the first mixer Q1018 (SPM5001),

21、as described previously. A portion of the RX VCO output is applied to the prescaler/swallow counter section in the PLL IC Q1052 (MB15A02PFV1). There the RX VCO signal is divided by 64 or 65, according to a con- trol signal from the Main CPU Q3014 (HD64F2238) on the CNTL Unit, before being applied to

22、 the programmable di- vider section of the PLL IC Q1052 (MB15A02PFV1). The data latch section of the PLL IC Q1052 (MB15A02PFV1) also receives serial dividing data from the Main CPU Q3014 (HD64F2238), which causes the pre- divided RX VCO signal to be further divided by 75,330 81,330 (or 60,264 65,064

23、) in the programmable divider section in the PLL IC Q1052 (MB15A02PFV1), depend- ing upon the desired receive frequency, so as to produce a 5 kHz (or 6.25 kHz) derivative of the current RX VCO frequency. Meanwhile, the reference divider section of the PLL IC Q1052 (MB15A02PFV1) divides the 14.4 MHz

24、crystal reference from the reference oscillator X1003 and Q1045 (2SC4116GR) by 2880 (or 2304) to produce the 5 kHz (or 6.25 kHz) loop reference. The 5 kHz or 6.25 kHz signal from the programmable di- vider (derived from the RX VCO) and that derived from the crystal are applied to the phase detector

25、section of the PLL IC Q1052 (MB15A02PFV1), which produces a pulsed output with pulse duration depending on the phase dif- ference between the input signals. This pulse train is then converted to DC, low pass filtered, then fed back to the RX VCO varactor diodes D1018/D1019 and D1020/D1021 (all 1SV28

26、2). Changes in the DC voltage applied to the varactor diodes D1018/D1019 and D1020/D1021 (all 1SV282) affect the reactance in the tank circuit RX VCO Q1048/1049 (both 2SK508), changing the oscillating frequency according to the phase difference between the signals derived from the RX VCO and the cry

27、stal reference oscillator. The RX VCO is thus phase-locked to the reference frequency standard. TRANSMIT SIGNAL PATH The speech audio from the CNTL Unit is applied to the varactor diode D1010 (HVU350), which frequency modu- lates the TX VCO from the unmodulated carrier at the transmit frequency. The

28、 modulated transmit signal is buff- ered by Q1026 (2SC5226), then passes through the RF am- plifier Q1030 (2SC3357) and RF diode switch D1016 (RN739F) to the PA Unit. The transmit signal is applied to the RF amplifier Q5001 (2SC3357) and Q5008 (PD55008), then finally amplified by power amplifier Q50

29、15 and Q5016 (both PD55025S) up to 50 Watts. Harmonic and spurious radiation in the final output is suppressed by a low pass filter consisting of coils L5007 L5010, plus capacitors C5071, C5078, C5082, C5085, and C5088 on the PA Unit, before delivery to the TX antenna jack. TX PLL AND VCO CIRCUITS T

30、he Transmitters PLL circuitry consists of PLL subsystem IC Q1008 (MB15A02PFV1) on the MAIN Unit, which con- tains a reference oscillator/divider, serial-to-parallel data latch, programmable divider, phase comparator and a swallow counter. Stability is obtained by a regulated 5 VDC supply via Q1062 (

31、L78M05T) and temperature com- pensated 14.4 MHz crystal oscillator X1001. The TX VCO, consisting of FET Q1021 (2SK508) and var- actor diodes D1008 and D1009 (both 1SV282), oscillates between 450 MHz and 490 MHz according to the pro- grammed transmit frequency. The theory of operation of the remainde

32、r of the PLL circuitry is similar to that of the RX PLL circuit; however, dividing data from the Main CPU Q3014 (HD64F2238) on the CNTL Unit is such that the VCO frequency is the actual transmit frequency. APC (AUTOMATIC POWER CONTROL) RF power output from the final amplifier Q5015/Q5016 (both PD550

33、25S) is sampled by C5061/C5056 and is then rectified by D5007 and D5008 (both HSM88AS). The re- sulting DC voltage is applied to the comparator Q5005 (TA75S01F), where the voltage is compared with a refer- ence voltage from the Main CPU Q3014 (HD64F2238) on the CNTL Unit, to produce a control voltag

34、e for the Auto- matic Power Controller Q5004 (2SC4116GR) and Q5002 (2SB1122S), which regulates supply voltage to Q5001 (2SC3357). Circuit Description F-2 CNTL (CONTROL ) U NIT The CNTL Unit consists of 8-bit CPU Q3014 (HD64F2238), EEPROM Q3006 (BR24L32F), RX and TX speech audio circuits, and various

35、 analog switches for the CPU and re- peater interconnections. Microprocessor operational code is stored in Q3006 (BR24L32F), while channel data and repeater configura- tion information is programmed from an external PC con- nected to the front panels MIC jack via a VPL-1 program- ming cable. The out

36、put from the Main CPU Q3014 (HD64F2238) con- tains serial control data used for REPEATER/BASE mode control, as well as TX and RX PLL data. Crystal X3002 oscillates at 12.288 MHz, and provides stable clock tim- ing for the Main CPU. When the repeater is powered on, the voltage at pin 62 of Q3014 (HD6

37、4F2238) becomes sta- ble, and the output of voltage detector IC Q3012 (BD4845FVE), which is tied to pin 59 (RST) of Q3014 (HD64F2238) becomes high, resetting the Main CPU. BASE OPERATION (TX, MIC-INPUT AUDIO) Microphone input is delivered past the MIC MUTE switch Q4002 (DTC323TK), then passes throug

38、h the audio am- plifier and active high pass filter at Q4001 (NJM2902V) when the signal is processed in the same manner as previ- ously described. Circuit Description F-3 Circuit Description F-4 Note Introduction The VXR-9000 has been aligned at the factory for the spec- ified performance across the

39、 entire frequency range spec- ified. Realignment should therefore not be necessary ex- cept in the event of a component failure. All component replacement and service should be performed only by an authorized Vertex Standard representative, or the warran- ty policy may be voided. The following proce

40、dures cover the sometimes critical and tedious adjustments that are not normally required once the transceiver has left the factory. However, if damage occurs and some parts are replaced, realignment may be required. If a sudden problem occurs during normal op- eration, it is likely due to component

41、 failure; realignment should not be done until after the faulty component has been replaced. We recommend that servicing be performed only by au- thorized Vertex Standard service technicians who are ex- perienced with the circuitry and fully equipped for repair and alignment. Therefore, if a fault i

42、s suspected, contact the dealer from whom the transceiver was purchased for instructions regarding repair. Authorized Vertex Standard service technicians realign all circuits and make complete performance checks to ensure compliance with factory specifications after replacing any faulty components.

43、Those who do undertake any of the following alignments are cautioned to proceed at their own risk. Problems caused by unauthorized attempts at realignment are not covered by the warranty policy. Also, Vertex Standard must reserve the right to change circuits and alignment procedures in the interest

44、of improved performance, with- out notifying owners. Under no circumstances should any alignment be attempted unless the normal function and operation of the transceiver are clearly understood, the cause of the malfunction has been clearly pinpointed and any faulty components replaced, and the need

45、for realign- ment determined to be absolutely necessary. The follow- ing test equipment (and thorough familiarity with its cor- rect use) is necessary for complete realignment. Correc- tion of problems caused by misalignment resulting from use of improper test equipment is not covered under the warr

46、anty policy. While most steps do not require all of the equipment listed, the interactions of some adjustments may require that more complex adjustments be performed afterwards. Do not attempt to perform only a single step unless it is clearly isolated electrically from all other steps. Have all tes

47、t equipment ready before beginning, and fol- low all of the steps in a section in the order presented. Required Test Equipment ? RF Signal Generator with calibrated output level at 1 GHz ? AF Signal Generator ? Frequency Counter: 0.2 ppm accuracy at 1 GHz ? In-line Wattmeter with 5% accuracy at 1 GH

48、z ? 50-ohm, 50-W RF Dummy Load ? Regulated DC Power Supply (standard 13.6V DC, 15A) ? AC Voltmeter ? DC Voltmeter ? UHF Sampling Coupler ? Microsoft Windows 98 or later operating system ? Vertex Standard VPL-1 Connection Cable and CE60 Alignment program Alignment Preparation when all items are align

49、ed, it is strongly recommend- ed to align according to following order. The detail infor- mation is written in the help of CE60 (Clone Editor). 1.RX VCO Tune Voltage (RX VCO) 2.TX VCO Tune Voltage (TX VCO) 3.PLL Reference Frequency (Frequency) 4.RX Sensitivity (RX Tune) 5.Squelch (SQL) 6.TX Power 7.Modulation Balance 8.Modulation Balance 9.Maximum Deviation 10. Maximum Deviation 11. Sub-Audio (CTCSS/DCS) Deviation CHANNELSFREQUENCY (SIMPLEX) Band-LOW450.000 MHz Band-MID470.000 MHz Band-HIGH490.000 MHz The