Vertex_VXR-9000_VHF_serv.pdf

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1、2006 VERTEX STANDARD CO., LTD. EC044N90B Rack Mount Repeater VXR-9000 (VHF) Service Manual Specifications .A-1 DSUB 25-pin Accessory Connector. B-1 Exploded View all adjustments can be performed from the personal computer, using with the Vertex Standard VPL-1 Programming Cable and CE60 Software. Whi

2、le we believe the information in this manual to be correct, Vertex Standard assumes no liability for damage that may occur as a result of typographical or other errors that may be present. Your cooperation in pointing out any inconsistencies in the technical information would be appreciated. Content

3、s Board Units (Schematics, Layouts 2SK520) and Q1053 (High Band; 2SK520) and varactor diodes D1018, D1019, D1020, and D1021 (Low Band; all 1SV229) and D1027, D1028, D1029, and D1030 (High Band; all 1SV229), according to the pro- grammed receiving frequency; the local signal then pass- es through buf

4、fer amplifier Q1059 (2SC5226) and first local amplifier Q1019 (2SC3357) to the first mixer Q1018 (SPM5001). The 73.35 MHz first IF signal is applied to monolithic crys- tal filters XF1001/XF1002 (Wide; TM7050A MF73P) or XF1501/XF1502 (Narrow; TM7050A MF73P) which strip away unwanted mixer products,

5、and the IF signal is ap- plied to the first IF amplifiers Q1022 (Wide; 2SC5226) or Q1502 (Narrow; 2SC5226). The amplified first IF signal is then delivered to the FM IF subsystem IC Q1028 (TA31136FN), which contains the second mixer, second local oscillator, limiter amplifier, noise amplifier, and F

6、M detector. A 2nd local oscillator signal, generated by the 72.895 MHz crystal X1002, produces the 455 kHz second IF signal when mixed with the first IF signal within Q1028 (TA31136FN). The second IF signal passes through ceramic filter CF1001 (CFWM455G) or CF1002 (CFWM455F) which strips away all bu

7、t the desired signal, and then passes through the limiter amplifier within Q1028 (TA31136FN) to ceramic discriminator CD1001 (CDB455C7), which removes any amplitude variations in the 455 kHz IF signal before de- tection of speech. The detected audio passes through the low pass filter, consisting of

8、R1199 and C1244, which re- jects the 455 kHz IF component. Circuit Description The audio signal from the MAIN Unit is delivered to the CNTL Unit and passes through the audio amplifier Q1020 (NJM2904V) to the active high pass filter section of Q3020 (FX805LG), which rejects the sub-audible frequency

9、com- ponent. The filtered audio signal is delivered to electron- ic volume Q1056 (M51132FP), which adjusts the audio sensitivity to compensate for audio level variations, then passes through audio amplifier Q1020 (NJM2904V), au- dio switch Q1040 (BU4066BCFV), attenuator consisting of R1233, and limi

10、ter amplifier Q1050 (NJM2904V), to the electronic volume control Q1056 (M51132FP), where the maximum deviation is set. The audio signal subsequent- ly passes through the 3-section active low pass filter con- sisting of Q1017-1/-2/-3 (NJM2902V) and audio amplifi- er Q1001 (NJM2902V) to providing the

11、repeater transmit audio. A portion of the audio signal from the active high pass filter section of Q3020 (FX805LG) is de-emphasized by R3095 and C3080, providing a flat audio response. The filtered audio then passes through the active band pass filter Q3021 (NJM2902V) and audio mute gate Q3015 (DTC3

12、23TK) to audio power amplifier Q1057 (TDA2003), providing up to 2 Watts of audio power to the 8-ohm loud- speaker. Sub-Audible Signaling (DECODER) A portion of the audio signal from the audio amplifier Q1020 (NJM2904V) passes through the 3-section active low pass filter Q1025 (NJM2902V) and the low

13、pass fil- tering section of Q3020 (FX805LG) to separate the CTC- SS tones from the received audio signal. The CTCSS tones are sent to the CTCSS decoder section of Q3020 (FX805LG). When a CTCSS tone is received, the CTCSS information is delivered to pin 77 of Main CPU Q3014 (HD64F2238BFA13) from pin

14、4 and 8 of Q3020 (FX805LG) which compares the CTCSS tone with the pro- grammed tone. Another portion of the audio signal amplified by Q1020 (NJM2904V) passes through the 3-section active low pass filter Q3044 (NJM2902V) to separate the DCS codes from the received audio signal. The low pass filtered

15、signal passes through the phase detector Q3044 (NJM2902V) to pin 39 of Main CPU Q3014 (HD64F2238BFA13). When a DCS code is received, the Main CPU Q3014 (HD64F2238BFA13) compares the DCS code with the programmed code. If the received CTCSS tone or DCS code matches the pro- grammed tone or code, pin 4

16、 of the Main CPU Q3014 (HD64F2238BFA13) goes low, turning off the squelch switch Q3015 (DTC323TK) and passing the received au- dio signal to the audio power amplifier Q1057 (TDA2003). F-1 Squelch Control The squelch circuit consists of noise amplifier Q1033 (DTA144EE) and noise detector D1015 on the

17、 MAIN Unit, and control circuitry within Main CPU Q3014 (HD64F2238BFA13) on the CNTL Unit. When no carrier is received, noise at the output of the audio detector stage of Q1028 (TA31136FN) is amplified by Q1033 (DTA144EE), and then rectified by D1015 (MA143) to provide a DC control voltage for the s

18、quelch switch. The resulting DC voltage is delivered to pin 23 of J1005. The DC voltage from the MAIN Unit is delivered to the A-D analog input port (pin 51) of the Main CPU Q3014 (HD64F2238BFA13) on the CNTL Unit, which compares the squelch threshold level to that which is memorized in EEPROM Q3006

19、 (BR24L32F) or set by the front panel SQL control. RX PLL and VCO Circuits The receivers PLL circuitry consists of PLL subsystem IC Q1052 (MB15A02PFV1) on the MAIN Unit, which con- tains a reference oscillator/divider, serial-to-parallel data latch, programmable divider, phase comparator and a swall

20、ow counter. Stability is obtained by a regulated 5 V DC supply via Q1062 (L78M05T) and temperature com- pensated 14.4 MHz crystal oscillator X1003. The RX VCO made up two VCO circuit, one is Low-Band RX VCO, consisting of FET Q1048 (2SK520) and varac- tor diodes D1018, D1019, D1020, and D1021 (all 1

21、SV229), and another one is High-Band RX VCO, consisting of FET Q1053 (2SK520) and varactor diodes D1027, D1028, D1029 and D1030 (all 1SV229), oscillates between 221.35 MHz and 247.35 MHz according to the programmed re- ceiving frequency. The RX VCO output passes through buffer amplifier Q1059 (2SC52

22、26) and first local amplifi- er Q1019 (2SC3357) to the first mixer Q1018 (SPM5001), as described previously. A portion of the RX VCO output is applied to the prescaler/swallow counter section of PLL IC Q1052 (MB15A02PFV1). There the RX VCO signal is divided by 64 or 65, according to a control signal

23、 from the Main CPU Q3014 (HD64F2238BFA13) on the CNTL Unit, before being applied to the programmable divider sec- tion of PLL IC Q1052 (MB15A02PFV1). The data latch section of the PLL IC Q1052 (MB15A02PFV1) also receives serial dividing data from the Main CPU Q3014 (HD64F2238BFA13), which causes the

24、 pre-divided RX VCO signal to be further divided by 75,330 81,330 (or 60,264 65,064) in the programmable divider section of PLL IC Q1052 (MB15A02PFV1), de- pending upon the desired receive frequency, so as to pro- duce a 5 kHz (or 6.25 kHz) derivative of the current RX VCO frequency. Meanwhile, the

25、reference divider section of the PLL IC Q1052 (MB15A02PFV1) divides the 14.4 MHz crystal reference from the reference oscillator X1003 and Q1045 (2SC4116GR) by 2880 (or 2304) to produce the 5 kHz (or 6.25 kHz) loop reference. The 5 kHz or 6.25 kHz signal from the programmable di- vider (derived from

26、 the RX VCO) and that derived from the crystal are applied to the phase detector section of the PLL IC Q1052 (MB15A02PFV1), which produces a pulsed output with pulse duration depending on the phase dif- ference between the input signals. This pulse train is then converted to DC, low pass filtered, t

27、hen fed back to the RX VCO varactor diodes D1018, D1019, D1020, D1021, D1027, D1028, D1029, and D1030 (all 1SV229). Changes in the DC voltage applied to the varactor diodes D1018, D1019, D1020, D1021, D1027, D1028, D1029, and D1030 (all 1SV229) affect the reactance in the tank circuit RX VCO Q1048 a

28、nd Q1053(both 2SK520), changing the oscillating frequency according to the phase difference be- tween the signals derived from the RX VCO and the crys- tal reference oscillator. The RX VCO is thus phase-locked to the reference frequency standard. Transmit Signal Path The speech audio from the CNTL U

29、nit is applied to the varactor diode D1010 (1SV214), which frequency modu- lates the TX VCO from the unmodulated carrier at the transmit frequency. The modulated transmit signal is buff- ered by Q1026 (2SC5226), then passes through the RF amplifier Q1030 (2SC3357) and RF diode switch D1016 to the PA

30、 Unit. The transmit signal is applied to the RF amplifier Q5001 (2SC3357) and Q5008 (PD55008TR), then finally ampli- fied by power amplifier Q5015 and Q5016 (both PD55025S) up to 50 Watts. Harmonic and spurious radi- ation in the final output is suppressed by a low pass filter consisting of coils L5

31、007, L5008 and L5010, plus capaci- tors C5071, C5078, C5082, C5085, C5088 and C5125 on the PA Unit, before delivery to the TX antenna jack. Circuit Description F-2 TX PLL and VCO Circuits The transmitters PLL circuitry consists of PLL subsystem IC Q1008 (MB15A02PFV1) on the MAIN Unit, which con- tai

32、ns a reference oscillator/divider, serial-to-parallel data latch, programmable divider, phase comparator and a swallow counter. Stability is obtained by a regulated 5 V DC supply via Q1062 (L78M05T) and temperature com- pensated 14.4 MHz crystal oscillator X1001. The TX VCO consisting of transistor

33、Q1021 (2SC5107) and varactor diodes D1008 and D1009 (both HVU306) oscillates between 148 MHz and 174 MHz according to the programmed transmit frequency. The theory of oper- ation of the remainder of the PLL circuitry is similar to that of the RX PLL circuit; however, dividing data from the Main Q301

34、4 (HD64F2238BFA13) on the CNTL Unit is such that the VCO frequency is the actual transmit fre- quency. APC (Automatic Power Control) RF power output from the final amplifier Q5015 and Q5016 (both PD55025S) is sampled by C5056 and C5061, then rectified by D5007 and D5008 (both HSM88AS). The resulting

35、 DC voltage from the Main CPU Q3014 (HD64F2238BFA13) on the CNTL Unit, to produce a con- trol voltage for the Automatic Power Controller Q5004 (2SC4116GR) and Q5002 (2SB1122S), which regulates supply voltage to Q5001 (2SC3357). Circuit Description F-3 CNTL (Control) Unit The CNTL Unit consists of 8-

36、bit CPU Q3014 (HD64F2238BFA13), EEPROM Q3006 (BR24L32F), RX and TX speech audio circuits, and various analog switch- es for the CPU and repeater interconnections. Microprocessor operational code is stored in Q3006 (BR24L32F), while channel data and repeater configura- tion information is programmed

37、from an external PC con- nected to the front panels MIC jack via a VPL-1 program- ming cable. The output from the Main CPU Q3014 (HD64F2238BFA13) contains serial control data used for REPEATER/BASE mode control, as well as TX and RX PLL data. Crystal X3002 oscillates at 12.288 MHz, and pro- vides st

38、able clock timing for the Main CPU Q3014 (HD64F2238BFA13). When the repeater is powered on, the voltage at pin 62 of Q3014 (HD64F2238BFA13) be- comes stable, and the output of voltage detector IC Q3012 (BD4845FVE), which is tied to pin 59 (RST) of Q3014 (HD64F2238BFA13) becomes high, resetting the M

39、ain CPU. Base Operation (TX, Mic-Input Audio) Microphone input is delivered past the MIC MUTE switch Q4002 (DTC323TK), then passes through the audio am- plifier and active high pass filter at Q4001 (NJM2902V) when the signal is processed in the same manner as pre- viously described. Circuit Descript

40、ion F-4 Note Introduction The VXR-9000 has been aligned at the factory for the spec- ified performance across the entire frequency range spec- ified. Realignment should therefore not be necessary ex- cept in the event of a component failure. All component replacement and service should be performed

41、only by an authorized Vertex Standard representative, or the war- ranty policy may be voided. The following procedures cover the sometimes critical and tedious adjustments that are not normally required once the transceiver has left the factory. However, if damage occurs and some parts are replaced,

42、 realignment may be required. If a sudden problem occurs during normal op- eration, it is likely due to component failure; realignment should not be done until after the faulty component has been replaced. We recommend that servicing be performed only by au- thorized Vertex Standard service technici

43、ans who are ex- perienced with the circuitry and fully equipped for re- pair and alignment. Therefore, if a fault is suspected, con- tact the dealer from whom the transceiver was purchased for instructions regarding repair. Authorized Vertex Stan- dard service technicians realign all circuits and ma

44、ke com- plete performance checks to ensure compliance with fac- tory specifications after replacing any faulty components. Those who do undertake any of the following alignments are cautioned to proceed at their own risk. Problems caused by unauthorized attempts at realignment are not covered by the

45、 warranty policy. Also, Vertex Standard must reserve the right to change circuits and alignment procedures in the interest of improved performance, with- out notifying owners. Under no circumstances should any alignment be attempted unless the normal function and operation of the transceiver are cle

46、arly understood, the cause of the malfunction has been clearly pinpointed and any faulty components replaced, and the need for realign- ment determined to be absolutely necessary. The follow- ing test equipment (and thorough familiarity with its cor- rect use) is necessary for complete realignment.

47、Correc- tion of problems caused by misalignment resulting from use of improper test equipment is not covered under the warranty policy. While most steps do not require all of the equipment listed, the interactions of some adjustments may require that more complex adjustments be performed afterwards.

48、 Do not attempt to perform only a single step unless it is clearly isolated electrically from all other steps. Have all test equipment ready before beginning, and fol- low all of the steps in a section in the order presented. Alignment G-1 Required Test Equipment ? RF Signal Generator with calibrate

49、d output level at 500 MHz ? AF Signal Generator ? Frequency Counter: 0.2 ppm accuracy at 500 MHz ? In-line Wattmeter with 5% accuracy at 500 MHz ? 50-ohm, 50-W RF Dummy Load (50 W mode) or 50- ohm, 100-W RF Dummy Load (100 W mode) ? 13.6V Regulated DC Power Supply with capable up to 15A (50 W mode) or 30A (100 W mode). ? AC Voltmeter ? DC Voltmeter ? VHF Sampling Coupler ? Microsoft Windows 98 or later operating system ? Vertex Standard VPL-1 Connection Cable, FRB-4 Tun- ing I/F Box, and CE60 Programming S