Fluke Z8Pod 电路.pdf

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1、 Z8 Pod Adapter for the Fluke 9000-Series Troubleshooter May 23, 1984 收音机爱好者资料库 Ra d i o Fa n s .CN Table of Contents 1. Conventions Used in This Document . 1 2. Overview . 2 3. Pod Adapter Setup . 3 3.1. Drivability Checking Control (Mode Bit 4) . 3 3.2. P34 Control (Mode Bit 5) . 5 3.3. DS- and R/

2、W- Control (Mode Bits 6 and 7) . 5 4. Z8 Operations . 5 4.1. Accessing Port 0 . 6 4.2. Accessing Port 1 . 6 4.3. Accessing Port 2 . 7 4.4. Accessing Port 3 . 7 4.5. Accessing External Program Memory . 7 4.6. Accessing External Data Memory . 8 4.7. Sensing the Serial Input Pin . 8 4.8. Running Progra

3、ms in the Pod RAM . 8 5. Limitations . 9 5.1. Input Loading . 9 5.2. Output Drive Capability . 9 5.3. Clock Oscillator Characteristics . 10 5.4. External Access Timing . 11 Appendix A. Schematic Diagrams . A-1 Z8 Pod Adapter May 23, 1984 收音机爱好者资料库 Ra d i o Fa n s .CN Z8 Pod Adapter for the Fluke 900

4、0-Series Troubleshooters May 23, 1984 This document describes a pod adapter which enables the Fluke 9000-Series Micro-System Troubleshooters to be used for diagnosing Z8- based UUTs. A pod adapter is necessary because no actual pod for the Z8 is available. The adapter described here was originally d

5、eveloped for use with a particular UUT, the Fluke 8840A Digital Multimeter. But its functionality is general enough that it should be useful for many other Z8-based UUTs as well. The Z8 pod adapter is used in conjunction with a 9000-Series trou- bleshooter and a 9000A-8048 Interface Pod. The adapter

6、 is connected between the 8048 pod and the UUT. It creates Z8-compatible timing sig- nals from the 8048 signals that come from the pod. It also provides I/O pins beyong those of the 8048, so that all input and output functions of the Z8 can be simulated. While the pod adapter does not provide a per-

7、 fect imitation of an actual Z8 microprocessor, it is quite close. The differences and limitations are detaild in section 5. 1. Conventions Used in This Document Some I/O ports on the Z8 have the same names as ports on the 8048, even though their functions are unrelated. To avoid confusion between Z

8、8 ports and 8048 ports, we adopt the following convention: Unless explicitly stated otherwise, a mention of an I/O port or a signal refers to the Z8. All references to 8048 ports and signals will be clearly indicated. An I/O port name such as Port 2 refers to the port as a whole, i.e., all 8 bits. I

9、ndividual lines of a port are refered to by their port number and line number. For example, P34 refers to Port 3, line 4. The lines are numbered to correspond to their controlling bits in the Z8. Bit 0 is the least-significant bit. A nibble is 4 bits of an I/O prot. The low nibble of a port always c

10、onsists of lines 0-3, and the high nibble consists of lines 4-7. Signal names, unless otherwise indicated, refer to the Z8 signals. A minus sign at the end of a signal name indicates that the signal is active-low. For example, the signal DS- (pronounced D S bar) is the Z8 data strobe signal and is a

11、sserted when it is at a low level. All addresses and data in this document are expressed in hexade- cimal notation. Z8 Pod Adapter May 23, 1984 收音机爱好者资料库 Ra d i o Fa n s .CN Z8 Pod Adapter May 23, 1984 2. Overview Figure 1 shows a block diagram of the Z8 pod adapter. About half of the Z8 pins are su

12、pported by simple direct connections through the adapter to functionally similar pins on the 8048 pod. The adapter con- nects the 8048 Bus port directly to the Z8 I/O port 1 pins. Similarly, it connects 8048 I/O Port 1 directly to Z8 Port 2. Finally, the VCC, GND, XTAL1, XTAL2, and RESET- signals ar

13、e passed directly through the adapter. _ 8048 Z8 +-+ | | | +-+ +-+ | | | 8243 | | | | Port 2| I/O | |Port 0 | | | Expander | | | | | | +-+ | Isolation |Port 3 | | | | | | | +-+ | Network |-|DS- | | | 8243 | | |-|AS- | |=| I/O |R/W- | | | Expander | | | | | | +-+ +-+ | | | / | | | +-+ | | | |=| | | |

14、 PSEN- |-| Timing | | | RD- |-| and |=| | WR- |-| Control | | ALE |-| | | | +-+ | | | Bus |Port 1 | | Port l|Port 2 | | RESET-|RESET- XTALl |XTAL1 XTAL2 |XTAL2 VCC |VCC GND |GND | | +-+ Figure 1. Pod Adapter Block Diagram. _ Page 2 收音机爱好者资料库 Ra d i o Fa n s .CN Z8 Pod Adapter May 23, 1984 The remain

15、der of the Z8 signals have to be created or derived by circuitry in the pod adapter. Sixteen of these, the I/O lines for Z8 Ports 0 and 3, are provided by an 8243 I/O Expander chip which is con- trolled by 8048 signals. The final 3 signals are control lines which are derived from 8048 control signal

16、s. A second 8243 I/O Expander provides inputs for sensing the actual levels of I/O and control signals. This sensing capability makes it possible to check the drivability of lines which are connected to logic in the pod adapter. Signals which are directly connected to the pod undergo automatic driva

17、bility checking within the pod. All Z8 pins which connect to logic in the pod adapter pass first through an isolation network which helps to protect the adapter from transients an illegal voltage levels in the UUT. Those Z8 signals which connect directly to equivalent 8040 pins are isolated in the p

18、od itself. 3. Pod Adapter Setup The pod adapter has a number of modes which affect the way it operates. These modes permit the pod adapter to be used with a fairly wide range of UUTs. They also allow certain drivability checks to be performed which would otherwise be impossible. Before attempting to

19、 access I/O ports or external devices, the user must set up the pod adapter modes to conform to the configuration of the particular UUT to which the adapter is connected. All of the pod adapter nodes are con- trolled by bits in the Mode Register, whose layout is shown in Figure 2. The Mode Register

20、can be written or read at troubleshooter address 2002. The following sections describe the functions of the Mode Register bits. 3.1. Drivability Checking Control (Mode Bit 4) Each time a new value is written to Port l or Port 2, the trouble- shooter automatically senses the levels of the ports I/O l

21、ines and com- pares the actual levels with the values written. Any discrepancy is reported as a drivability error. This automatic drivability checking function is built into the pod. It works correctly on Ports l and 2 even with the pod adapter in place, because those ports are passed directly throu

22、gh the pod adapter without any intervening circuitry. In contrast, Ports 0 and 3 as well as some of the control lines are driven by logic internal to the pod adapter. The troubleshooter cannot directly check the drivability of those lines. Since drivability checking is an important diagnostic functi

23、on, the pod adapter contains extra circuitry to permit checking the drivability of Port 0, Port 3, and the DS- and R/W- signals. The extra circuitry allows actua1 output levels to be read back and compared with the desired levels. The checking is not automatic, however; it must be done manually thro

24、ugh manipulation of Mode Bit 4. For normal troubleshooting operations, Mode Bit 4 should be 0. When Mode Bit 4 is 0, reads and writes at addresses 2004-2007 will result in input and output operations on Ports 0 and 3, as described in section 4. Page 3 收音机爱好者资料库 Ra d i o Fa n s .CN Z8 Pod Adapter May

25、 23, 1984 _ +-+-+-+-+-+-+-+-+ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | +-+-+-+-+-+-+-+-+ | X | X | X | X | Unused +-+-+-+-+-+ | 0 | Addr. 2004-2007 normal I/O +-+ | 1 | Addr. 2004-2007 drivability checking +-+-+ | 0 | P34 is latched output pin +-+ | 1 | P34 is DM- output +-+-+ | 0 | DS- output forced low +

26、-+ | 1 | DS- output normal function +-+-+ | 0 | R/W- output forced low +-+ | l | R/W- output normal function +-+ Figure 2. Mode Register Layout. _ When values have been written to one or more of these addresses, the actual output levels can be read back after setting Mode Bit 4 to 1. When Mode Bit 4

27、 is 1, previously written values are maintained on the output pins while a separate data path is enabled for reading the actual levels. Here is the procedure for outputting a new value and checking the drivability: 1. Clear Mode Bit 4 to 0 by writing to address 2002. 2. Write desired value to addres

28、s 2004, 2005, or 2007. 3. Set Mode Bit 4 to 1 by writing to address 2002. 4. Read actual value from the same address as step 2. Bits whose actual value differs from the desired value correspond to lines that could not be driven. The attentive reader will notice that the above procedure does not appl

29、y to address 2006, the low-order nibble of Port 3. That nibble is restricted by the Z8 hardware to input operations only, so writing to address 2006 is illegal. Without an output capability, drivability checking is meaningless, and it is not provided for the low nibble of Port 3. Instead, a read ope

30、ration from address 2006 when Mode Bit 4 is 1 will return the actual levels present on the DS- and R/W- control lines, as shown in Figure 3. When used in conjunction with Mode Bits 6 and 7 as described below, this feature permits checking the drivability of the DS- and R/W- lines. Page 4 收音机爱好者资料库 R

31、a d i o Fa n s .CN Z8 Pod Adapter May 23, 1984 _ +-+-+-+-+ | 3 | 2 | 1 | 0 | +-+-+-+-+ | 0 | DS- = 0 (asserted) +-+ | 1 | DS- = 1 (not asserted) +-+-+ | 0 | R/W- = 0 (write) +-+ | 1 | R/W- = 1 (read) +-+-+-+ | X | X | Undefined +-+-+ Figure 3. Value from address 2006 when Mode Bit 4 is 1. _ To outpu

32、t a new value to Port 0 or Port 3, Mode Bit 4 must be 0. Writes to these ports are illegal when Mode Bit 4 is 1. 3.2. P34 Control (Mode Bit 5) Pln P34 (Port 3, bit 4) serves a dual function on the Z8. For sys- tems without external data memory or peripherals, it is typically used as a general-purpos

33、e latched output pin. For larger systems this pin can be made to output the DM- signal, which serves to distinguish between external program and data memory accesses. The pod adapter sup- ports P34 in both of these roles. The function of P34 is selected by Mode Bit 5. When Mode Bit 5 is 0, P34 serve

34、s as a normal output pin which is controlled (along with pins P35-P37) by write operations to address 2007. When Mode Bit 5 is 1, P34 outputs the DM- signal. 3.3. DS- and R/W- Control (Mode Bits 6 and 7) Mode Bits 6 and 7 should both be set to 1 for normal troubleshoot- ing operations. When cleared

35、to 0, these bits serve to force the DS- (bit 6) and the R/W- (bit 7) signals to the low state. This capability is provided so that the drivability of DS- and R/W- may be checked con- veniently. The drivability of these pins is checked by selectively forcing them to 0, then reading their actual level

36、s from address 2006 with Mode Bit 4 set to 1. Note that the quiescent state of each of these signals is 1, so there is no need to be able to force them high. 4. Z8 Operations The pod adapter is capable of reading and/or writing the Z8 I/O pins as well as memory and I/O devices external to the Z8. Al

37、l accesses are made by read or write operations from the troubleshooter. The legal troubleshooter addresses and their functions are listed in Table 1. The functions are described in more detail in the following sections. Page 5 收音机爱好者资料库 Ra d i o Fa n s .CN Z8 Pod Adapter May 23, 1984 _ Table l. Add

38、ress Space Assignment. ADDRESS FUNCTION ADDRESSED 0000-0FFF External Program Memory 1100-11FF External Data Memory 2000 Z8 Port 1 2001 Z8 Port 2 2002 Pod Adapter Mode 2004 Z8 Port 0, low nibble 2005 Z8 Port 0, high nibble 2006 Z8 Port 3, low nibble 2007 Z8 Port 3, high nibble 3000-30FF Executable Po

39、d RAM _ 4.1. Accessing Port 0 Port 0 is accessed as two independent nibbles, at troubleshooter addresses 2004 (lines P00-P03) and 2005 (lines P04-P07). Each nibble may be configured as 4 input lines or 4 output lines. Mode Bit 4 must be 0 for normal input and output operations on Port 0. Reading from address 2004 or 2005 configures the corresponding nib- ble as an input, and reads the levels of its lines. Writing to address 2004 or 2005 configures the corresponding nibble as an output, and latches the data onto its lines. After data has been ou