171(Model171_Multimeter) 电路图.pdf

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1、Instruction Manual Model 171 Digital Multimeter 01997, Keithley Instruments, Inc. Cleveland, Ohio, U.S.A. RadioFans.CN 收音机爱 好者资料库 KEITHLEY INSTRUMENTS. 1 N C. INSTRUCTION MANUAL MODEL 171 DIGITAL MULTIMETER RadioFans.CN 收音机爱 好者资料库 CONTENTS SECTION PAGE SECTION PAGE Title Page . 1 contents . ii IAt o

2、f Illusfratlons. . iii specifications . iv 1. General Description 1-1. Inrraduceion . 1 1-2. warranty InformLion . 1 1-3. Change Notice. . 1 1-4. Features . 1 2. operation 2-1. Measurement Considerations . : 2-2. Ca*ecfianB. . 2-3. Controls . 5 2-4. Digital Display. . 5 2-5. operation 88 a Voltmeter

3、 . 5 2-6. operaeion as an Amnlerer. . 2-7. Operation as an Ohmmeter . 2 2-8. Overloade. . 2-9. Digital Outputs and Controls . . z 2-10. Operating Technique. . 10 3. Circuit Description 3-1. General. . 13 3-2. Analog Amplifier . 13 3-3. Switching. . 14 3-4. Driven Guard Amplifier . 15 3-5. Protection

4、 ctrcits. . 15 3-6. Fncfion and Range Display . 15 3-7. Digital Section. . 15 3-8. Power supply . 18 4. Accessories 4-l. General. . 20 4-2. operating Instructions . 20 4-3. Model 1712 wal output. . 20 4-4. Model 1713 Extender Card . 20 4-5. Model 1007 Dual Rack Mounring Kit 20 4-6. Model 2000 Rack M

5、ounting Kit . . 21 5. Maintenance 5-1. General. . 2 7. 5-2. Required Test Equipme. . 22 5-3. Performance Checks . 22 5-4. Adjustment and C.libration . 26 5-5. Component and Calibration Layouts. 34 6. Replaceable Parts 6-1. General. . 40 6-2. EleCtrical schematics and Diagrams 40 6-3. HOW to se the P

6、arts List. . 40 6-4. How to Order Parts . 40 6-5. Chassis Paru List . 41 6-6. Electrical Part* I 20.2% of reading 0” LiW IO-merohm ranees: ,1.3% Of readine a1 the 1o-meeohm range; +20% or reading on the lOOO-megohm *ange (?0.02% Of range an all ranges). TEMPEKATURE COEFFICIENT: +(0.008% of reading +

7、o.oo?.% of ranee +0.0003% of readine r,er memhm/C. SETTLING-TIME: Less than 2 appropriate decimal location; function in engineering units; polarity and overload indicarion; 2 readings/second. ISOLATION: Circuit ground to chassis ground: greater than 100 megoihms shunted by Less than 0.02 micro- fara

8、d. Circuit ground may be Eloaced up co 500 volt with respect to chassis ground in all modes. Maxim safe voltage between input and chassis ground: 1500 volts peak. WARMUP TIME: 45 minutes co within twice soecified CONNECTORS: Input, chassis ground; binding posts. Analog OUtput; Amphenol 80-PC2F. POWE

9、R: 105-125 or 210-250 volts (switch selecred), 50-6 HZ, 25 watts. 1 i. 3. ) s m 9 1 DIMENSIONS,WEIGHT: Style M 3-l/2 in. half-rack, over- all bench size 4 in. high x 8-l/2 in. wide x 15-l/4 in. deep (100 x 217 x 385 mm). Net weight, 10 pound (4,6 kg). ACCESSORIES SPPLIED: Mating OUtpUt connector, sp

10、are input fuse. iv 773 I MODEL 171 SECTION 1. GENERAL DESCRIPTION 773 General Description Paragraph Turns on instrument power 2-3a sets dc-voltage functian 2-3c set.5 ac-voltage function 2-3c sets ohms function 2-3c Sets dc-ampere function 2-3c sets ac-ampere function 2-3c sets instrument sensiii.vi

11、ty 2-3b 2-h 2-h Z-2a GENERAL “ESCKIPTION TABLE l-2. kar Panel Controls and Connectors FUSE 117”: l/2 ampere 2.LOa 234”: l/4 ampere OUTPUT BCD OUTP”T LINE Input Analog output, 1v for full range Provides digital outputs with Model 1712 installed as shown (connector not provided without Model 1712) rec

12、eptacle mates with 3-wire line cord 2-2h 2-9a ?-lI, or purchased separately in kit form for field install- ation. The Model 1712 includes an output-buffet module, w-wired 50-pin receptacle (5108), wiring harnses, and mating 50-pin connector (not wired). C. OUtput Connector Pin Identification. Refer

13、to Table 2-7 and Figure 5. The 50-1 i” BCD-output receptacle (5108) of the Mod 51 171 i.s arl Amphenol Micro-Ribbon type 57-40500 (Ke*thle, 7 CS-221). The supplied mating connector is an Amphenol Micro- 773 MODEL 171 TABLE 2-6. Specifications Model 1712 Digital output 1 OIGITAI. OUTPUT: BCD (8421) o

14、pen collector lo- gic (Motorola MC 858P) represents each of 4 digits (0000=0), overrange digit, overload (“l”), polarity (+ = “l”), function and four decimal positions. TIMING OUTPUTS: Clock: 100 kHz pulses. CO”nf Interval: Logic “0” appears during count interval (i.e. pulse width is propor- tional

15、to analog input signal). Flag (Fx): Logic “1” (“0”) appears for a 300-m*ll*second interval out of a co”“ers*o” time of 500 milliseconds. No change in digital output is made during this interval. OUTPUT LOGIC LEVELS: 0”fp”t Logic “1” - open transistor collector to ground with leas than 100 microamper

16、es leakage. +12 volts maximum allowable applied voltage. output Logic “0” : transistor switch closure to ground with less than 0.5-volt saturation voleage at f35 milliamperes sink current. REMOTE CONTROLS: a: 8 lines permit ward serializina in 4-bit increments or multiples thereof. “pen circuit inhi

17、bita controlled output lines from conducting (closure enables conduction). Hold: Closure retains result of last con”ersion in both the digital output and the display. Hold 112: Closure hairs co”“ersions at end of present conversion holding reading in bath the digital outpuf and the dis- play. w: Rel

18、ease edge of pulsed closure initiates one con”ers*o” when in Hold 112. Signal is averaged for a ZOO- nrillisecond period starting 100 milli- seconds after release of “Trifiger” or Hold 112. Flag Reset: Closure sets Flag (Flag) to logic “0” (“1”). mqumm CONTROI. LOGIC LEVEL: open circuit - either gre

19、ater than 4 kilohms resistance or a voltage between +2 and +12 Volts (except flag reset, +5 voles maximum) referenced to ground. Closure = closure to graund within 0.5 volt while sinking c2.5 milliamperes. CONNECTOR: Output: 50-pin Amphenol Micro- Ribbon type 57-40500. ACCESSORIES *“AILABLE: Model 4

20、405 Terminal BOX: 3 ft. (Im) cable, Connecfor, and 50-terminal box. Model 1801 output Cable: 10 ft. (3m) cable,wich 5%pi” connectors and mating panel-mount co*nector. 773 OPERATION Ribbon type 57-30500 (Keichley cs-220). The optional Model 4405 Terminal BOX and Model 1801 output Cable (see Table 2-6

21、) are i +I2 volts maximum allowable applied voltage. Logic state “0” is defined as a transistor switch closure to ground with less rhn” 0.5 “OlL saturation voltage at + 35 milllmaperes sink current. The “open collector” feature of the Model 1712 Digital OUtpUt is compatible with a wide variety of lo

22、gic types including Tn., “TL, and RIL. In the case of RTL and some aeher logic types, a pull-up resistor CR) is needed tcJ define logic state “1”. For more information on digital interfacing. contact your Keithley Represenrative or the factory for your copy of our ProdUCt Notes “interfacing Digital

23、Instruments”. It encompasses not only the basics of digital coding, but also the types of logic in use today by most digital equipment ma”“- facturers including Krithley. quence of the overall analog-to-digital (A-to-D) con- version cycle in relationship with the 1712 Digital output. 1. Integrate Pe

24、riod. During the “INTEGRATE” period, the analog signal is applied to the in- tegrating amplifier. The ramp waveform of the “INTEGRATOR” could have a posfti”e or negative slope, depending on the polarity of the input signal. MODEL 171 “P” r- - r- - 1 1 j 1 j 1 lNPT, ;i -1 1 *v,x, *V, I R R -I i i STR

25、OBE a-t Y- i + kWUTLo, il SECTION 3. CIRCUIT DESCRIPTION 1” 1. v I” 10 In” 4.99k:I 499 k. 100 100 mv 4.99k.Y 39.2k. 10 1 v 4.99k 0 1 I 10 ” 4.99lc: 0 1 100 ” 4.99kl: 0 I 1000 ” 4.99kcn 0 1 FIGURE 11. AC/DC Co”“erter. MODEL 171 MODEL 171 input drop is 1 volt instead of 0.1 volr. uiodes input drop is

26、1 volt instead of 0.1 volr. uiodes 01003 and “1002 are protection diodes to prevent aver- 01003 and “1002 are protection diodes to prevent aver- loadini: Of the ohms reicrence circuit in the event loadini: Of the ohms reicrence circuit in the event FIGURE 12. Ohmmeter Configuration. i. Frequency Div

27、ider. This circuit provides the chopping frequency as derived from the 1” kHz clock race. Integrated circuit QA506 divides down the clock rate by a factor of 11. Inteerared circuit 9.4507 (A, 8).is a dual flip-flop whh, provides an additional X4 division which results in a chopping frequency of 227.

28、27 Hz. U”ffU Amplifier. This circuir provides drive signals for the switching transistors in the modu- lator and demodulator circuits. Transisrars 9508 and Q507 provide anti-phase square waves which drive the gates of the switching FETs Q501 and Q502. Transismr Q5O6 provides a drive signal far Trans

29、istor Switch 9505. Potentiometer R535 is an internal adjust- ment for calibration of the chopper drive signal. 3-3. SWITCHING. a. Function Selection. me five front panel pusi,- buttons are used LO select either DC”, AC”, OHMS, DCA, or ACA. 1. a. When this mode is selected the input ,I is connected t

30、hru B divider to the analog amplifier input. The divider is used on the I”“, 1”“, and 1 kV ranges. The divider ratios are l/10, 1/l”“, and l/1000 respectively to give a 1 volt input to the analog amplifier.See Figure 13. 7 Range Shunt it Volt sensitivity ndjustmc” 1 Llri 100 kil 100 rn” 10 ,A 10 !a

31、100 m” 1.00 llii I k$i 100 rn” ImA 100 12 100 “1” 10 mh 1” $2 100 ,“” 100 “IA I !I 100 “3” 1000 IVA 0.1 $1 JO” a” The Integrator is zeroed for a minimum of 100 milliseconds (ZERO period) before the sampling is repeated. me total conversion time is 500 millisecands, which corresponds to 2 conversions

32、 per second. 3. me A-to-D cOnerter is composed of six ma,ar circuits as follows: (See Figure 16 for a block diagram.) a). Clock (located on PC-300). 2. Timing sequence. me operation of rile A-to-D Converter can be described by considering a typical conversion cycle. b). BCD Counter (located on K-299

33、). c,). Program/Decoder (located on P-299). a). me clock provides pulses at rate of 100 kHZ for 50 to 60 Hz operation. b). The *CD counter serves as a master timing control for the A-to-D conversion cycle. The timing is accomplished by the 10000 counter which has five coded states, namely 0,1,2,3, a

34、nd 4, each lasting for 10,000 COtS of the 100 !dlz clock. e) . when the Buffer/Store command is given, the Buffer/Storage Register copies the BCD in- formafion from the BCD Counter (Qb.208, QA211, QA214, QA217). f). The conversion cycle is completed after the 2 period (i.e., the Zeroing Period). d).

35、 Integrator (located on R-301). e). zero-crossing Detecmr (located on PC-301). f). Buffer/Storage Register (located on K-299). 4. Circuitry. a). Clock. An oscillator composed of integra- ted circuits QA401A, 8, c provides clock pulses at a rate of 100 kHz. A crystal oscillator Y401 determines the fr

36、equency Of operation. b) BCD counter. The Decade counters designa- ted 1. lo, loo, and 1000 are campoaed of individual integrated circuit modules QA217, Q.4214, QA211, and QA208 respectively. All four counters have B capacity of lo-counts each. FOX COnts of 10,000 and higher, the overrange 1 m201) i

37、s lit. This is accomplished by Q201 and QAZOZA. c). Program/Decoder. This circuit produces event commands to control the overall sequence for the conversion cycle. The Program/Decoder consists of a 5-state counter (OA207). loeic circuits QA204D, QA203D, QA205Ei; E, iid F; and inverter Q.42064. me ev

38、ent commands are defined as O,l, !2, 3,4n. d). Integrator. The operation Of rile 1ntegrarm is controlled by switches identified as s*, SD, Sx, and SR as shown in Figure 15. Swirch Sx (Sampling Switch) is composed of Q302. Switch LL (zeroing switch) is composed of transistors Q305 and 4315. Tramistor

39、s Q306, Q307 are control CIRCUIT LmxRIPTION circuits controling 4305 and 9315. The integrator amplifier consists of QA301 and Q313. This is fallowed by a gain of 20 and gain of 50 (QA302 and QA303). The integrator capacitor is C312 (.1 pfd). Switches Q308 and Q31O control the reference current durin

40、g the “0,l” period. The feedback rezeroing of the InteSraor circuit is performed by FET Q315 (Switch SD). Keistor R351 and capacitor c317 provide filtering in the feedback loop. Diodes 0312 and 0313 provide fast response for large input offsets (especially due t” input overloads). e). Zero-Crossing

41、Detector. The level detector is QA304. Its output provides two levels Which selects the proper reference for the “0,l” period and also produces a zero crossing pulse (p). fl. Buffer/Storage Register. The “I”, “10”. “loo”, and “1000” storage registers are composed of individual integrated circuits lc

42、uits decode tic BC” lnfornlatlo” irom the storage Register into ten-line decimal code. A separate driver circuit controls the “overrange 1” whenever the full range exceeds 9-9-9-9. 1. Numerical Readouts. The four numerical readouts “204, “203, “202, and “201 are *riven by Decoder/Driver modules Q.42

43、19, QA216, QA213, and ()A210 respectively. Blanking of the *utner- ical readouts occurs whenever the display ex- ceeds 1-9-9-9-9. The Blanking circuit is composed of tranisturs Q204, Q205, and Q206. Transistor Q205 drives the base of Q204 to provide +I70 volts for the readout tubes during normal ope

44、r- ati.on. When an overload occurs, cransistar 0206 is driven “ON” which in turn reduces the +I70 volt output, thus blanking the readout tubes. 2. polarity Indication. This circuit is composed of integrated circuit QA205A, transistors 0202 and Q203, and polarity indicator module US202. Inte- grated

45、circuit ()A2028 is the Polariry SL0ra.w Register. 3. overrange indication. This circuit is com- posed of integrated circuits Qh201A and QUO%, transistm Q201, and indicator DS201. QA202A is the Overload Storage RegisCer. 773 d. Digital Output Option. The digital output includes output b”fferS for all

46、 output informatlo”. The buffers utilize “Open Collector” OUtput tran- sistors as shown in Figure 6. The buffer stages have provision for optional “STROBE” control as show” in Figure 16. Input 1 Input 2 OUtpUt I 773 SECTION 4. ACCESSORIES ,CI ,:;l”: 1: FIC”rn 17. f.fodcl 1007 Dual Rack Mounting Kit

47、- Exploded View. FIG”RE 18. Model 2000 Single Rack Mounting Kit. - Exploded View. 773 SECTION 5. MAINTENANCE 5-1. GENERAI. This section contains information necessary to maintain the i”str”me”t. Included are procedures ior performance checksand calibration. 5-2. P.EQ”1RE.o TEST EQUlPMENT. RecoIlunen

48、ded test equipment for checking and servicing the Model 171 are given in T. e). Steps a through d may be repeated if de- sired far Oscillator settings from dc to 180 HZ at 10 HZ multiples. 5108 for optional Digital OutpUt goes here (discard cover plate) PC-297 Function Display Board PC-303 Analog Board PC-304 Switch Board I I P$-300 Clock Board b . f PC-301 Integraror Board PC-305 Mother Board / 51202 Connector, ma