Crown_XLS_(3-Space)_Service_Notes电路图.pdf
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1、XLS 3U SERIES CIRCUIT DESCRIPTION AND SERVICE NOTES INTRODUCTION These notes are intended to assist maintenance and service of the XLS 3-rack-space family of amplifiers. Please refer to the relevant schematic diagrams and system diagram while reading this document. The component references of the tw
2、o amplifier channel electronics are appended A and B respectively. Shared circuitry (such as that of the protection system) has no suffix. This document will refer to channel A references only. Operation of channel B is identical except where explicitly noted. Voltage values in bold mentioned in the
3、 text are test voltages which may be used for diagnostic purposes. Please read the surrounding text which explains circuit operation and may qualify such measurements. MECHANICAL CONSTRUCTION The mechanical structure of the amplifier comprises three main components: chassis, front panel and cover. T
4、he one-piece chassis incorporates rear panel, side panels, bottom cover and transformer mount. The main PCB is fixed to the chassis using 4 M4x16 screws with insulating washers through the main heatsinks and 4 M4x8 screws for the edges of the board, one of which connects the chassis electrically to
5、0V on the PCB. There are two heatsinks secured to the board with 3x No6 / 5/16 pozi pan B point self tapping screws and 3x M3.5 shakeproof washers each. Output devices are bare mounted (with zinc oxide heatsink paste) to the heat- sinks with 2x No6 / 5/16 pozi pan B point self tapping screws each. C
6、AUTION: The heatsinks are LIVE at up to +95VDC on one AND -95VDC on the other. The plugable input module and output module are secured using 4x No4 / 8 plastite screws and 4x M3 / 8 screws respectively. The mechanical integrity of the amplifier is realised when the substantial frontpanel is fitted u
7、sing 4x M4 /10 Flange Pozi Black screws at the sides and 2x M4 nuts behind the front. The cover is secured using 6x #8 / 3/8 Flange Pozi Black self tapping screws. All internal wiring is plugable to allow quick removal of main PCB for repairs and servicing. CIRCUIT DESCRIPTION Input Stage The input
8、stage is built around one half of a TL072 dual operational amplifier, IC1A on the input board, configured as a unity-gain differential amplifier. Its correct operation depends on both of its input terminals being correctly terminated and, therefore, any gain errors around this stage may be a result
9、of a faulty cable termination within the mating XLR connectors. There is no provision for trimming Common-Mode Rejection (CMR) but checking this can easily eliminate the input stage in the search for a fault. RadioFans.CN 收音机爱 好者资料库 CMR checkout procedure is as follows : Inject a common-mode test si
10、gnal at 1kHz and +4dBu to the channel under test. The common-mode test signal of the Audio Precision test system is suitable, otherwise connect the signal to both pins 2 2) 15Hz: C11A and C12A connected in parallel with C8A and C10A respectively; 3) Off position: C14A bypassing C8A and C10A. Limiter
11、 switch SW2 in its OFF position shorts R2A and disconnects LDR1A to turn the Clip Limiter off. In its ON position, SW2 connects R2A and LDR1A as a light-dependent voltage divider, controlling the level of the input signal. LDR1A faces LED2A, which is lit when the amplifier reaches about 1dB below cl
12、ip (at the same time as the clip LED at the front). Because the resistance of LDR1A reduces as its cell area is illuminated, pushing the amplifier into clip will, therefore, cause the input signal to be reduced at the R2A -LDR1A divider. Thus the amplifier is Clip Limited. The output of the filterin
13、g/limiting op-amp is AC coupled by C13A and built out by R11A, and continues to pin 3 of Header 2 (ch. B pin 4 of Header 3), at which point it re-enters the main board and makes its way to pin 1 of CN2A, a three-pin header making connection by wire to the level potentiometers: pin 1 is Top, pin 2 is
14、 Wiper, pin 3 is Bottom. The signal emerges from pin 2 and is fed to the input of the Power Amplifier. POWER AMPLIFIER The power amplifier consists of a fairly conventional Class A driver stage driving a Class AB bipolar output stage. Each stage will be dealt with individually. Class A Driver The in
15、put signal returned from the level control is fed via DC blocking capacitor C7A and R8A. DC bias current for the Class A input stage is supplied via R9A, while 33pF capacitor C54A prevents any extreme high fre- quency input signals from reaching the power amplifier and also provides a low source imp
16、edance at high fre- quencies to ensure frequency stability. The first stage of the class A driver consists of Q1A and Q2A configured as a long-tailed pair differential RadioFans.CN 收音机爱 好者资料库 amplifier. Emitter resistors R10A and R11A de-sensitise the performance of the input stage to parameter vari
17、a- tions of the two input transistors. The quiescent current for the input stage is delivered by current source Q3A. Diodes D1A and D2A provide a reference voltage of approximately 1.2V, which is applied to the base of Q3A. Approximately half of this (0.6V) will then appear across R13A (220R), which
18、 then sets the current, sourced from Q3A collector at approximately 2.7mA. In the quiescent state half of this current is driven through Q1A and Q2A. Hence the voltage dropped across emitter resistors R10A and R11A will be approximately equal at 135mV. Overall voltage feedback of the amplifier is de
19、rived through R18A and R17A. R57A and C20A provide local feedback around the Class A section only to define the dominant pole of the amplifier. C56A connected in series with R66A gives 100% DC feedback to minimize any DC offset at the output. The reulting feedback signal is applied to the base of TR
20、53A. The collector currents of Q1A and Q2A are fed via D3A and D4A to R15A and R16A respectively. Hence, in the quiescent state, R15A and R16A should each exhibit a voltage drop of 1.35V or so. Under normal conditions, the signals at the bases of Q1A and Q2A will be identical. However, under fault c
21、ondi- tions, such as a DC offset at the output, the base voltages will become offset also. For example, in the event of a large DC offset of +50V at the output, a positive DC voltage will appear at the feedback point and hence at the base of Q2A. Although this would, in theory, be the full +50V, owi
22、ng to C11A being rated at only 25V, the voltage will, in practice, be somewhat lower. However, the important issue is that the voltage is positive. In the event the voltage is negative this indicates that the feedback network is faulty (most likely R18A itself). The voltage at Q2A base being positiv
23、e while the base of Q1A is close to 0V will then reverse bias Q2A base-emitter hence turning off the transistor. Hence, no voltage should appear across R11A and R16A while double the normal voltage will appear across R10A and R15A (270mV and 2.7V respectively). Should this not be the case, it indica
24、tes a fault in the input stage itself. The output of the input long-tailed-pair (i.e. the voltages at the anodes of D3A and D4A) are fed to a second long- tailed pair Q4A and Q5A. The bias current for this stage is set by resistor R19A thus: D3A drops approximately the same voltage as the base-emitt
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