Casio_CTK-500_Service_Manual电路图.pdf
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1、(with price) CTK-500 ELECTRONIC KEYBOARD R CTK-500 RadioFans.CN 收音机爱 好者资料库 - 2 - Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Circuit Description
2、. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Major Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PCB Views and Major Check Points . . . . . . . . . . . . . . . . . . . . . . . . 8 Schematic Diagrams . . . . . . . . . . . . .
3、. . . . . . . . . . . . . . . . . . . . . . . 9 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IC and Transistor Lead Identification . . . . . . . . . . . . . . . . . . . . . 12 Exploded View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4、. . . . . . . . . . 14 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CONTENTS RadioFans.CN 收音机爱 好者资料库 1 General Number of Keys:61 Polyphonic:16-note Preset Tones:120 Auto-Rhythms:40 Auto-Accompaniment:CASIO Chord/Fingered Jukebox Tunes:40 Cho
5、rd Memory:Real-Time Recording Memory Capacity: 128 chords (maximum) Built-In Speakers:12 cm dia. 1.1W Input Rating: 2 pcs. Terminals:Output Jack Output Impedance: 50 , Output Voltage: 1.4 V (rms)MAX, AC Adapter Jack (DC 9 V) Auto Power Off:Approximately 6 minutes after the last operation Power Sourc
6、e:2-way AC or DC source AC: AC adapter DC: 6 D size dry batteries Power Consumption:6.7 W Dimentions:110 x 939 x 337 mm (HWD) (4-5/16 x 36-15/16 x 13-1/4 inches) (HWD) Weight:4.5 kg (9.9 lbs) excluding batteries Electrical Current Drain with 9V DC: No Sound Output125 mA 30% Maximum Volume530 mA 30%
7、with keys C4 to D#5 pressed in Clarinet tone, Volume; Maximum, Rhythm; Samba, Tempo; Maximum Output Level (Vrms with 8 load each channel):107 mV 30% with key C4 pressed in Clarinet tone, Volume; Maximum Sound Pressure Level:107 dB 10 dB at 10 cm away from the speaker with key G6 in Brass-1 tone Mini
8、mum Operating Voltage:6.0 V SPECIFICATIONS RadioFans.CN 收音机爱 好者资料库 2 LEDs LED Driver IC3 KO0 KO5, KO17 OE CE A0 A16 D0 D15 43.45 MHz Clock Keys and Switches KO0 KO16 KI1 KI7 CPU MSM6626-01 LSI1 ROM MN232000CUQ LSI2 ROUT LOUT Reset IC S8053ANO IC4 KO18 (APO) VCCAVDDVDD Power Amp. LA4127 IC2 Output Po
9、wer IC CA5668 IC1 Filter (R) T5 Filter (L) T6 Speakers Main Volume Control X1 BLOCK DIAGRAM 3 CIRCUIT DESCRIPTION Key and Switch Matrix KI0KI1KI2KI3KI4KI5KI6KI7 KO0C2C#2D2D#2E2F2 KO1F#2G2G#2A2A#2B2 KO2C3C#3D3D#3E3F3 KO3F#3G3G#3A3A#3B3 KO4C4C#4D4D#4E4F4 KO5F#4G4G#4A4A#4B4 KO6C5C#5D5D#5E5F5 KO7F#5G5G#
10、5A5A#5B5 KO8C6C#6D6D#6E6F6 KO9F#6G6G#6A6A#6B6 KO10C7 Tempo Up Tempo Down KO11 Power Off NormalFingered CASIO Chord KO12 Accomp. Volume 1 (Min) Accomp. Volume 2 Accomp. Volume 3 Accomp. Volume 4 Accomp. Volume 5 (Max) KO13Reverb OffReverb 1Reverb 2 KO14 Synchro / Fill-In Start/Stop Intro/ Ending Chor
11、d Memory Record Chord Memory Play Ad-Lib Musician Jukebox Start/Stop Beat (Jukebox) KO15Bank ABank BBank CBank DBank EBank FBank GBank H KO16Number 1Number 2Number 3Number 4Number 5 Solo Sound Duo Sound Ensenble Sound 4 F#3 G#3 A#3C#4 D#4F#4 G#4 A#4 C#5 D#5F#5G#5 A#5 F3G3A3B3C4D4E4F4G4A4B4C5D5E5F5G5
12、A5B5C6 D#3 C2D2E2F2G2A2B2C3D3E3B6A6G6F6E6D6C7 C#3A#2G#2F#2D#2C#2A#6G#6F#6D#6C#6 CPU (LSI1: MSM6626-01) The CPU reads sound data from the ROM in accordance with the pressed key and the selected tone; the CPU can read rhythm data simultaneously when a rhythm pattern is selected. Then it provides the l
13、eft and the right channels waveforms separately, by converting the data into the waveforms with two built-in DACs. The CPU also controls keys, switches, and LEDs. The following table shows the pin functions of LSI1. Pin No.TerminalIn/OutFunction 1 10 74 80 KO0 KO16Out Using time sharing, the termina
14、ls provide key and switch scan signals, and LED drive signals. 11KO17Out Clock output for the LED driver 12KO18 (APO)Out APO (Auto Power Off) signal output. 13KO20Out Not used. 14 21KI0 KI7In Input terminals from the keys and switches 22-MIIn Power ON trigger pulse input. 23-RESETIn CPU reset signal
15、 input. 24REFHIn Low level reference voltage input for the built-in DAC 25AVDDIn +5 V source for the built-in DAC 26ROUTOut Right channel sound signal output 27LOUTOut Left channel sound signal output 28AGNDIn Ground (0 V) source for the built-in DAC 29REFLIn High level reference voltage for the bui
16、lt-in DAC 30, 31TEST1, TEST2 Not used. Connected to ground. 32GNDIn Ground (0 V) source 33, 34COSI, COSOIn/Out 43.45 MHz clock input/output 35VDDIn +5 V DC source. Regardless of the power switch position, the terminal always receives +5 V DC. 36-CEOut Chip enable signal output. Low effective. 37-OEO
17、ut Read enable signal output. Low effective. 38 40ADR17 ADR19Out Not used. 41 57ADR0 ADR16Out Address bus for the ROM 58 73DIN0 DIN15In Data bus for the ROM Nomenclature of Keys 5 From the CPU To main volume FIlter Block Since the sound signall from the CPU is a stepped waveform, the filter block is
18、 added to smooth the waveform. VDD 1K AGAGAG 10K 10K6.2K C562(H) C222(H) C331J 2SC3112B VDD CPU MSM6626-01 LSI1 VDD ON OFF ON OFF MI KO11 KI1 KI0 Power Switch ON KO18 APO signal OFF: 0V ON: +5 V Power On/Off Circuit When the power switch is turned on, a low level differential pulse is provided to te
19、rminal MI of the CPU. Upon receipt of the pulse, the CPU starts the power ON sequence and raises the APO signal to +5 V. When the switch is off, on receiving the KO11 signal at terminal KI0, the CPU drops the APO signal to ground level to shut down power. Initial Reset Circuit When batteries are set
20、 or an AC adapter is connected, the reset IC provides a low pulse to the CPU. The CPU then initializes its internal circuit. VDD Battery set RESET CPU MSM6626-01 LSI1 Reset IC S8053ANO IC4 6 Power IC (IC1: CA5668) The power IC generates three voltages AVDD (+5 V) for the CPU and the reset IC, AVDD (
21、+5 V) for the analog circuit, and VCC (+9 V) for the power amplifier. VDD (+5 V) is always generated, but AVDD (+5 V) and VCC (+ 9V) are controlled by the APO signal. KO0 KO1 KO2 KO3 KO4 KO5 KO17 D3 D5 D2 D6 D1 D4 Q3 Q5 Q2 Q6 Q1 Q4 L0 L1 L2 L3 L4 L5 CPU MSM6626-01 LSI1 LED Driver TC74CH174AP IC3 Cho
22、rd Memory Play Solo Sound Duo Sound Ensenble Sound Beat (Jukebox) Ad-Lib Musician VDD CLK CLR LED Driving VDD AVDD VCC APO VIN VDIN GND CA5668 IC1 +9V APOVDDAVDDVCC 0 V+5 V0 V0 V +5 V+5 V+5 V +9 V 7 MAJOR WAVEFORMS 8 1 2356 789 101112134 PCB VIEWS AND MAJOR CHECK POINTS Volume PCB M5505-MA2M Main PC
23、B M5505-MA1M 9 6 7 3 2 5 8 9 13 11 4 1 12 10 M5505-MA1M,MA2M PCB SCHEMATIC DIAGRAMS 10 Keyboard PCBs M619K-KY1M,KY2M PCB-M619K-KY1MPCB-M619K-KY2M 11 TROUBLESHOOTING Nature of TroubleFaulty BlockCheckpoint No powerPower Jack (J1)Jack contact. Power IC (IC1: CA5668)Pin 8 should have +5 V. Pin 6 should
24、 provide + 5V when pin 10 receives + 5 V. Reset IC (IC4: S8053ANO) Pin 1 should provide a low level pulse when an AC adapter is connected. Power Switch Pin 22 of CPU should receive a trigger pulse when turning on the switch. Main Clock Generator (X1)Check oscillation at pin 34 of CPU. CPU (LSI1: MSM
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