midas_xl3电路图.pdf
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1、1 Operators it is protected from R.F. contamination by R48/C41 and R53/C44, and from over-voltage by diode bridge D13-16. IC5 is a differential amplifier whose common mode rejection is factory set by VR3 to maximum at 100Hz, typically 85dB. The insert return is fed via C47 to SW6 (INSERT) and from h
2、ere to the EQ in/out switch SW7. After returning from the equaliser section, a signal is fed to the meter via ST3, the SOLO switch SW8 via buffer IC6b and the VCA section via either Jumper ST4/pre or IC19a. VCA and Mute The mute control is detailed later. Two mutes are associated with the vca stage,
3、 pre-fade and post-fade. These can be selected as required by jumpers in ST4 and ST5. The options are shown on diagram XL301_LK.DGM. The vca is based around IC6a, IC7 and IC8a in the audio path and IC8b in the control path. The control voltage from either the internal module level control RV3 (if fi
4、tted) and the fader tray level control are summed with an offset voltage by IC8b. This offset voltage adjusted by VR6 is used to define the available vca control range. It has been preset in the factory and should not require adjusting unless the vca has been replaced. The output voltage of IC8b, an
5、d therefore the control range of the vca, is further clamped by D58 and D59 to prevent overshoot. The VCA output is routed either pre or post mute (dependent upon ST5) to the pan control RV14a/RV14b which offers 3dB of attenuation at pan centre Diagram XL301_4.DGM. The pan control is buffered by IC1
6、6a and IC16b and then fed to the left and right master busses via the fet switches Q27-30 activated by SW5 (MASTER ON) Diagram. XL301_M.DGM. The outputs from IC16a and IC16b are also fed to the SOLO switch SW8 for routing to the solo busses. The feeds for the mixes are derived from the VCA input (Pi
7、n 1 of IC6) and the muted vca output. These are buffered by IC17a IC3c has 30dB of gain, which enables D1-D10 to turn on 30dB ahead of D11-D20. Transistor Q1 provides a regulated power source for the LM3915s and transistors Q2 and Q3 are constant current sources for the LED chains. To calibrate the
8、meter, a signal of -30dB is applied at pin 1 of ST1 the level can be externally verified at whichever output is driving the meter, selected by the meter change-over switch S34, and the cathode of D23 is monitored by an oscilloscope. When a symmetrical trace is obtained by adjusting VR1, the level is
9、 increased to 0dB and VR2 is adjusted so that D13 the 0dB yellow LED just illuminates. Then the signal is reduced to -30dB, when the LED chain should have only the first three LEDs D1-D3 illuminated. If the calibration appears to be wrong, the symmetry should be rechecked. Solo Routing Diagram XL310
10、_A3.DGM (both groups). Each of the four pfl switches, two per group (mix PFL and direct in PFL), provide a gate signal to select the appropriate fet switches for the source. These four gate signals are summed by diodes D51 to D54 and are used to turn on fet Q14 routing the pfl signal to the pfl buss
11、 via connector B pin 10. They are also used to route the left and right solo buss feeds from IC15 via fets Q10 and Q13 to connector B pins 11 (left) and 12 (right). In addition to this the signal is inverted by transistor Q15 in order to drive transistor Q16. Q16 is used to activate the Solo_Gate li
12、ne via connector B pin 13. In the case of channel A, the two group solo?s are switched by Q8 and Q9 into the summing input of IC15a via R111 and R112 to give unity gain. Likewise for channel B with Q11 this transposes the signals from the solo and master summing stages. IC4 is the balancing network
13、for the insert send which appears at connector A (STA) pins 19 hot and 20 cold, it is protected from excess voltage by the diode bridge D1-4, and set for maximum common mode rejection at 100Hz by VR1 typically 85dB. The insert return appears at connector A pins 21 hot and 22 cold; it is protected fr
14、om R.F. contamination by R21/C18 and R26/C21, and from over-voltage by diode bridge D5-8. IC5 is a differential amplifier whose common mode rejection is factory set by VR2 to maximum at 100Hz, typically 85dB. Block b of the insert switch S2 selects pre-insert signal from RLY1 or post-insert signal f
15、rom C24 and feeds it to block b of the master output PFL switch S3 change to diagram XL320_3.DGM, and via JP?A? to the master output fader RV1. The non-inverting buffer IC12a feeds both the meter via the meter changeover switch S8 and the mute switch S4. The inverting input of IC12a is fed via conne
16、ctor B pin 12s solder side only with talk signals from the communications module. The mute switch S4 wiper feeds the output stage IC6, which is protected from excess voltage by the diode bridge D9-12, and set for maximum common mode rejection at 100Hz by VR3 typically 85dB. Matrix Output Diagram XL3
17、20_2.DGM. Matrix signals arrive via connector B pins 10 and 11 signal and 7 ground at the virtual earth summing stage IC7b, and are reinverted by IC7a. IC8 is the balancing network for the insert send which appears at connector A pins 6 hot and 7 cold, it is protected from excess voltage by the diod
18、e bridge D13-16, and set for maximum common mode rejection at 100Hz by VR4 typically 85dB. The insert return appears at connector A pins 8 hot and 9 cold; it is protected from R.F. contamination by R50/C47 and R55/C50, and from over-voltage by diode bridge D17-20. IC9 is a differential amplifier who
19、se common mode rejection is factory set by VR5 to maximum at 100Hz, typically 85dB. Block b of the insert switch S5 selects pre-insert signal from C37 or post-insert signal from C53 and feeds it to block b of the matrix output PFL switch S6 15 Diagram XL320_3.DGM, and via JP?C? to the matrix output
20、fader RV2. The non-inverting buffer IC13a feeds both the meter via the meter changeover switch S8 and the mute switch S7. The inverting input of IC13a is fed via connector B pin 12 component side only with talk signals from the communications module. The mute switch S7 wiper feeds the output stage I
21、C10, which is protected from excess voltage by the diode bridge D21-24, and set for maximum common mode rejection at 100Hz by VR6 typically 85dB. Record Output Diagram XL320_2.DGM. The record outputs share one level control and one level check switch which overrides whichever input has been selected
22、 by the meter changeover switch S8 on diagram XL320_3.DGM. The controls are linked by the ribbon connector between ST2a on the lower (left) PBC and ST2b on the upper (right) PCB, but in all other respects each output is entirely separate. Signal is derived from the wiper of the master mute switch S4
23、 diagram XL320_3.DGM and fed to the top of the level control RV3a (left) or b (right), from the wiper of which it passes through a non-inverting buffer IC14b. From here the signal is fed both to the check level switch S9a or b via C66, and to the output stage IC11a, which is protected from excess vo
24、ltage by the diode bridge D25-28, and set for maximum common mode rejection at 100Hz by VR7 typically 85dB. Output Meter Diagram XL20M.DGM. IC3a and b receive, rectify, and calibrate the signal fed from the master module via connector ST1. The signal, now a varying positive voltage, is fed to IC3c a
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