ORBAN 2200 Manual Section 6 电路图.pdf

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1、Section 6 Technical Data pagecontents 6-2Specifications 6-5Circuit Description 6-5Overview 6-516.384MHz Oscillator and System Clocking 6-7Control Circuits 6-9User Control Interface and LED Display Circuits 6-10L/R Input Circuits 6-13L/R Output Circuits 6-17Composite Output Circuits 6-18DSP Circuits

2、6-20Power Supply 6-22Parts List 6-23Obtaining Spare Parts 6-40Vendor Codes 6-41Schematics, Assembly Drawings 6-57Abbreviations OPTIMOD-FM 2200TECHNICAL DATA 6-1 RadioFans.CN 收音机爱 好者资料库 page Specifications It is impossible to characterize the listening quality of even the simplest limiter or compres-

3、 sor on the basis of the usual specifications, because such specifications cannot adequately describe the crucial dynamic processes that occur under program conditions. Therefore, the only way to meaningfully evaluate the sound of an audio processor is by subjective listening tests. Certain specific

4、ations are presented here to assure the engineer that they are reasonable, to help plan the installation, and to help make certain comparisons with other processing equipment. Some specifications are for features that are only available on the 2200-D. Installation Analog Audio Input Configuration: L

5、eft and right. Impedance: Electronically balanced 600 or 10k load impedance, jumper-selectable. Dynamic Range: 90dB. Common Mode Rejection: 70dB at 50-60Hz. 45dB at 60Hz-15kHz. Sensitivity: 20dBu to +20dBu to produce 10dB gain reduction at 1kHz, software- and jumper- adjustable. Maximum Input Level:

6、 +27dBu. Connector: XLR-type, female, EMI-suppressed. Pin 1 Chassis Ground, Pins 2 (+) and 3 electronically balanced, floating and symmetrical. A/D Conversion: 18-bit. Filtering: RFI-filtered, with high-pass filter at 0.15Hz. Analog Audio Output Configuration: Left and right. Flat or pre-emphasized

7、(at 50s or 75s), software-selectable. Source Impedance: 30, 5%, electronically balanced and floating. Load Impedance: 600 or greater, balanced or unbalanced. Termination not required. Output Level: Adjustable from 20dBu to +20dBu into 600 or greater load, software-adjust- able. Output Noise Level: 9

8、0.0dB (Bypass mode, de-emphasized, 20Hz-15kHz bandwidth, ref- erenced to 100% modulation). Crosstalk: 70dB, 20Hz-15kHz. Distortion: 0.05% THD (Bypass mode, de-emphasized, 20Hz-15kHz bandwidth). Connector: XLR-type, male, EMI-suppressed. Pin 1 Chassis Ground, Pins 2 (+) and 3 elec- tronically balance

9、d, floating and symmetrical. Filtering: RFI-filtered. 6-2 TECHNICAL DATA OPTIMOD-FM 2200 RadioFans.CN 收音机爱 好者资料库 Digital Audio Input (2200-D Only) Configuration: Two-channel per AES/EBU-standard. 20-bit resolution. Sampling rate: 25-55kHz, automatically-selected. Connector: XLR-type, female, EMI-sup

10、pressed. Pin 1 Chassis Ground, Pins 2 and 3 trans- former balanced and floating. Input Reference Level: Adjustable from 0dBFS to 20dBFS, software-controlled. Digital Audio Output (2200-D Only) Configuration: Two-channel AES/EBU-standard. 18-bit resolution. Software-controllable for flat, pre-emphasi

11、zed to the selected processing pre-emphasis, J.17 pre-emphasized, or pre-emphasized to the selected processing pre-emphasis plus J.17 pre-emphasis. Sampling rate: 32kHz, 44.1kHz, or 48kHz, software-selected. Connector: XLR-type, male, EMI-suppressed. Pin 1 Chassis Ground, Pins 2 and 3 transformer ba

12、lanced and floating. Status Bits: AES/EBU status bits are implemented to control pre-emphasis in the Orban 8208 digital Stereo Encoder. Output Level Adjustment Output at 100% modulation, adjustable from 0dBFS to 22.8dBFS, software-controlled. Composite Baseband Outputs Configuration: Two (2) outputs

13、, each with an independent output level control, output amplifier and connector. Source Impedance: 0 voltage source or 75 (jumper-selectable), single ended, floating over chassis ground. Load Impedance: 37 or greater. Termination not required. Level (0 Source Impedance, 75 or higher Load Impedance):

14、 Adjustable 0.4Vp-p to 8.8Vp-p with front panel multi-turn output level controls, one per output. Pilot Level: Adjustable from 8% to 10%, software-controlled. Pilot Stability: 19kHz, 0.5Hz (10 to 40 C). D/A Conversion: 18-bit. Signal-to-Noise Ratio: 85dB (Bypass mode, demodulataed, de-emphasized, 20

15、Hz-80kHz bandwidth, referenced to 100% modulation, unweighted). Distortion: 0.05% THD (Bypass mode, demodulated, de-emphasized, 20Hz-15kHz band- width, referenced to 100% modulation, unweighted). Stereo Separation: At 100% modulation = 3.5Vp-p, 60dB, 30Hz-15kHz, 65dB typical at 1kHz; at 100% modulat

16、ion = 1.0Vp-p, 50dB, 30Hz-15kHz. Crosstalk (Linear): 80dB, main channel to sub-channel or sub-channel to main channel) referenced to 100% modulation). Crosstalk (Non-Linear): 80dB, main channel to sub-channel or sub-channel to main chan- nel) referenced to 100% modulation). 38kHz Suppression: 70dB;

17、75dB typical (referenced to 100% modulation). OPTIMOD-FM 2200TECHNICAL DATA 6-3 RadioFans.CN 收音机爱 好者资料库 76kHz and Sideband Suppression: 70dB; 80dB typical (referenced to 100% modulation). Connector: BNC, floating over chassis ground. EMI-suppressed. Maximum Load Capacitance: 0.047F (0 source impedan

18、ce). Maximum Recommended Cable Length (0 Source Impedance): 100ft/30m RG-58A/U. Filtering: RFI-filtered. Remote Control Interface Configuration: Eight opto-isolated inputs, user-programmable to select any eight of: User Presets, Factory Presets, Bypass, Tone, Exit Test (returns from Bypass or Tone),

19、 Stereo, Mono from Left, Mono from Right, Mono from Sum, Input Analog, Input Digital. Control: Momentary or continuous low side contact closure. 10mA minimum sink current; 9VDC, 50mA rating. Power Supply: Current-Limited 9VDC provided to facilitate use with contact closure. Connector: DB-25, EMI-sup

20、pressed. Filtering: RFI-Filtered. Power Voltage: 90-120VAC, 100-132VAC or 200-264VAC, 50-60Hz; 40VA. Connector: IEC; detachable 3-wire power cord supplied. AC is EMI-suppressed. Ground: Circuit ground is independent of chassis ground; can be isolated or connected with a rear panel switch. Safety Sta

21、ndards: UL, CE, CSA. Environmental Operating Temperature Range: 32 to 122F/0 to 50C at nominal operating voltages. Humidity: 0-95% RH, non-condensing. Dimensions (W x D x H ): 19“ x 14.25” x 1.75“/48.3cm x 36.2cm x 4.5cm. 1 rack unit high. Weight: 12 lbs/5.4kg. Shipping Weight: 15 lbs/6.8kg. Warrant

22、y One Year, Parts and Labor: Subject to the limitations set forth in Orbans Standard Warranty Agreement. Specifications are subject to change without notice. 6-4 TECHNICAL DATA OPTIMOD-FM 2200 Circuit Description This section provides a detailed description of circuits used in the 2200/2200-D. It st

23、arts with an overview of the 2200/2200-D system, identifying circuit sections and describing their purpose. Then each section is treated in detail by first giving an overview of the circuits followed by a component-by-component description. Keywords are highlighted throughout the circuit description

24、s to help you quickly locate the information you need. Overview The block diagram on page 6-35 illustrates the following overview of 2200/2200-D circuit sections. The 16.384MHz Oscillator and System Clocking section provides the various clocks needed by the control, I/O and DSP circuits to carry out

25、 their functions. The Control Circuits administrate control of the 2200/2200-D system. The User Control Interface and LED Display Circuits section includes the connector, RF-filtering, and circuitry for the remote control inputs. It also includes circuitry for the front panel pushbutton switches, LE

26、D control status indicators, and LED Meters. The LED Meters measure various 2200/2200-D signal levels and display the results on six front panel 10-segment LED meters. The L/R Input Circuits include the connectors and RF-filtering for the left and right audio inputs and the digital audio input, and

27、the circuitry to interface these inputs to the digital processing. The L/R Output Circuits include the connectors and RF-filtering for the left and right audio outputs and the digital audio output, and the circuitry to interface the digital processing to these outputs. The Composite Output Circuits

28、include the connectors and RF-filtering for the two compos- ite outputs, and the circuitry to interface the digitally processed, stereo encoded signal to these outputs. The DSP Circuits implement the bypass, test tone, audio processing, and stereo encoding functions using digital signal processing.

29、The Power Supply provides power for all 2200/2200-D circuit sections. 16.384MHz Oscillator and System Clocking A synchronous clocking scheme is used on the 2200/2200-D to eliminate any asynchronous clocks operating in the sensitive regions of the L/R input A/D converter. A single 16.384MHz crystal o

30、scillator provides the timing reference for all system digital clock signals. The only clocks that run asynchronous to this clock are the AES/EBU digital audio input related clocks and the 11.2896MHz free running crystal clock oscillator providing the OPTIMOD-FM 2200TECHNICAL DATA 6-5 44.1kHz AES/EB

31、U output sample rate (this does not fall within a sensitive region of the A/D). Synchronous counters are used to divide the 16.384MHz clock to produce the various clock signals for the system. A PLL circuit is used to synthesize an 18.432MHz clock for operating the host microprocessor and a 6.144MHz

32、 clock for providing the 48kHz AES/EBU output sample rate clock in addition to providing the AES/EBU input receiver with the ability to measure the input sample rate. Component-Level Description: The 16.384MHz digital output from crystal oscillator Y602 feeds the master clock (MCLK) inputs of both t

33、he input and the output SRC chips IC603 and IC615. The 16.384MHz clock also feeds flip-flop IC604, which divides by two to produce an 8.192MHz clock. The 8.192MHz clock feeds digital multiplexer chip IC610, which routes the 8.192MHz to AES/EBU digital audio transmitter chip IC616 when an internally

34、generated 32kHz output sample rate is selected. The 8.192MHz clock is also sent to an 8-bit synchronous counter implemented in programmable logic array (PLA) IC613. This counter divides down to obtain the lower frequency system clocks. All outputs of the PLA have their transitions coincident with th

35、e rising edge of the 8.192MHz clock. The 8.192MHz clock is inverted by buffers IC605-A, -B to provide clocks 8.192MHZA* and 8.192MHZB* that have falling edges coinci- dent with the transitions of the lower frequency clocks. 8.192MHZA* feeds the bit clock of the inter-DSP communication links followin

36、g buffers IC710-B, -D. 8.192MHZB* feeds the A/D input clock (256 x sample rate), the L/R output D/A master clock, and the input bit clock on both the L/R output D/A and the composite D/A. The 2.048MHz clock output from IC613 feeds the PLL circuit made up of PLA IC618, 74HC4046 phase detector/VCO IC6

37、19 and associated components. The PLA first buffers the 2.048MHz signal, providing a clean 2.048MHz output at pin 12 used as the reference input to the PLL phase detector (IC619 pin 14). Of the three detectors included in the 74HC4046, the phase frequency detector (PFD) is used by the 2200/2200-D. T

38、he output of the phase detector (pin 13) feeds the loop filter made up of resistors R607, R608 and capacitor C605 that provide a single pole low-pass filter forming a second order loop. Pin 9 of IC619 is the input control voltage to the VCO. Resistor R614 eliminates subharmonic frequency modulation

39、of the VCO caused by parasitic capacitance. Resistors R605 and R606 set the PLLs lock-in frequency range. A divide-by-nine counter is placed between the VCO output and the phase detector comparator input. This places the VCO output at 18.432MHz. The divide-by-nine is implemented by the PLA IC618 bet

40、ween pins 2 and 15. A 6.144MHz clock is derived at the counters divide-by-three point and is provided at pin 17 of the PLA. The PLA provides a buffered 18.432MHz output at pin 14 which feeds Z-180 microprocessor IC100. IC614-A, -D provide buffered clocks 2.048MHZA and 2.048MHZB for driving the EXTAL

41、 inputs (pin 27) of the DSP chips. Each buffer drives four DSP chips. The 256kHz clock output of IC613 (pin 15) is required for the DSP-to-composite D/A interface. The 128kHz clock (pin 14) is used for the inter-DSP word clock. The 128kHz, 64kHz and 32kHz clocks are all used in the LCD backlight dri

42、ve 6-6 TECHNICAL DATA OPTIMOD-FM 2200 circuit. The 32kHz clock is also used for the input word clock of both the output sample-rate converter (SRC) and the L/R output D/A. The 32kHz clock is used to generate DSP interrupt request signals (IRQBA, IRQBB) required for process timing and interchip synch

43、ronization. The circuit consisting of flip-flop IC612 and IC614-B, -C is required to ensure that the first falling edges of all IRQB signals are coincident. This synchronization occurs every time the unit is powered up and when there is a processing algorithm change. It is controlled by the Z-180 vi

44、a pin 2 of latch IC611. The 32kHz clock is also used, along with IC313, in the A/D clock synchronizing circuit. This circuit makes the IRQB and the L/R clocks, both operating at 32kHz, phase synchronous. This ensures that the process-to- output buffer transfer internal to the DSP doesnt overlap the

45、output buffer-to-pe- ripheral transfer. The 8.192MHZB* clock that feeds the A/D input clock (IC312 pin 19) is internally divided down to produce a 32kHz word clock at IC312 pin 13 and a 2.048MHz bit clock at pin 14. These clocks are used to control the A/D-to-DSP serial interface and the input SRC-t

46、o-DSP serial interface. AC terminations are used on various clocks throughout the board to improve signal integrity for sensitive devices. Control Circuits The control circuits process and execute user-initiated requests to the system. The source of these requests is the front panel buttons and the

47、remote contact closures. These changes affect hardware function and/or DSP processing. The control circuits also send information to the LCD display, LED status, and LED meter circuits. A RAM chip stores code segments. For quick access, an EEPROM chip stores dynamic system state information. A ROM c

48、hip contains the executable form of 2200/2200-D DSP and Control software. 1.Microprocessor and Power Monitoring Circuit A Z-180 microprocessor executes software code required to control the functionality of the 2200/2200-D. The EXTAL port of the Z-180 receives an 18.432MHz clock signal from the cloc

49、k divider/PLL circuit and is internally divided down to 9.216MHz to provide the Z-180 system clock frequency. ROM contains control software for the Z-180. User system setup and other dynamic system state information that must survive power down is stored in non-volatile EEPROM. Power monitoring circuitry prevents data corruption by placing and holding the Z-180 in reset if AC mains power is insufficient. The Z-180 communicates to the DSP through the synchronous serial data host port. When the DSP requires executable code, the Z-180 reads it from the ROM and sends it to the DSP. The Z-1