Line 6 Spider II 15 Watt Amplifier Schematic 电路图.pdf
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1、RadioFans.CN 收音机爱 好者资料库 RadioFans.CN 收音机爱 好者资料库 CONFIDENTIAL Spider II 3012/1508 Theory of Operation August 29, 2004 -Guitar input section- Analog signal consideration: An analog signal is input through jack J5, and is referenced to ground by R1 which establishes a 1Meg Ohm input impedance. Maximum
2、input signal amplitude before clipping is about 5Vpp(0 to 200Hz). The signal then passes to U1-A, where the signal is buffered, and also amplified by the pre- emphasis filter in the feedback loop (R3 R4 and C1) This single-pole pre-emphasis filter adds gain starting around 200Hz. Maximum gain is abo
3、ut 8dB at 20kHz. The output of U1-A is the “low gain” analog signal and is sent to the left input of the CODEC U2. It is also sent to the input of U1-B. U1-B increases the “low gain” signal by a gain of 16, and this resulting “high gain” signal is then sent to the Right channel of the CODEC U2. Digi
4、tal signal consideration: The GUITAR_SENSE signal, which is sent to the DSP, indicates the presence of a jack plugged into J1. This signal is created by: J1 and the pull-up resistor R37. The signal is low if there is no jack, and high if a jack is plugged in. EMI consideration: C72 and GF1 help to s
5、hunt HF noise to the chassis and AGND appropriately. ESD consideration: D2 is a voltage clamp, and helps insure that ESD will not exceed the voltage rails of U1. R2 provides over-voltage current limiting for both D5 and U14. -Signal Processing Section- Analog signal consideration: Inputs to ADC: The
6、 “high gain” and “low gain” analog signals arrive at the CODEC from the Guitar In Section. The series capacitors on each input are used as “DC blocking” capacitors since the analog inputs of U2 are biased to approximately of its analog supply, or 1.5V. On the right channel “high gain” input to U2, a
7、 diode D10 is used to “clamp” the voltage to a safe level (- 06.V and +3VA+0.6V) since this channel is usually clipping with a nominal signal present at the input. Spider II Theory of OperationLine 6 confidential. Page 1 of 1 The ADC of U2 converts the left and right analog signals into digital sign
8、als, which are then sent to the DSP (ADC_DATA) for processing. Only one of the signals is chosen based on amplitude, before it is processed. The processing includes a digital de-emphasis filter to compliment the analog pre-emphasis filter. Outputs of DAC: The codec receives the processed digital aud
9、io signal from the DSP at its serial data input (DAC_DATA). The codec then converts the digital signal into analog signals, which are output on pins 15-16 of U2. The analog outputs of codec U13 are differential, and have a DC bias of approximately +3.3VA (about 1.5V). C14-15 are used as DC blocking
10、caps. The output signals are summed in order to gain 3dB of noise performance because our system is mono for this product. The signal then is passed to U9-A, which is configured as a low-pass filter with gain of around 4.1. The frequency cutoff for the LPF is well above the audio pass-band. (fc20kHz
11、) and is intended to reduce EMI. The resulting output of U9A (+AUDIO_L) is single-ended, and in- phase with the systems input. J2 is configured as an auxiliary CD/MP3 input. The L/R signals are summed mono via R45 and R47 and mixed with our CODEC output at U9-A. U9-B is configured as a buffer betwee
12、n the master volume and the power amp input. Digital signal consideration: System reset is provided internally by the MCU. The MCU provides system control and ADC for all of the front panel potentiometers. The DSP U5 provides processing of the audio signals. Clocks: The 3.6864MHz system master clock
13、 is composed of the components connected to pin 55 (EXTAL) of U7. All other clocks are generated from the master clock within U5, using a PLL. The filter for the PLL is made up of the components connected to pins 31 and 32 of U7. CODEC clocks: The codec clocks are generated by U5. Since the system s
14、ampling frequency (fs) is 39.0625 kHz, this is the frequency of the LRCLK. BCLK is the bit clock and runs at a speed of 64fs, or 2.5MHz. Finally, the codec master clock, or MCLK, runs at 256fs, or 10MHz. Memories: There is one SRAM connected to the DSP. The SRAM U7 is used for buffering processed au
15、dio signals. FBV: The floorboard signals are buffered through U6. The signals are serial differential output and single ended input. Diodes D25-27 provide ESD/over-voltage protection for U6. LEDS: The MCU pulls the cathode of an LED on the U.I. low to turn it on. Resistors R6,13,15,19,29 limit curre
16、nt to the LEDS. JTAG: The JTAG port of the DSP is available through the uninstalled H2 header. This connection is used for development and in-house software upgrades. Midi/Development I/O: H3 is used to interface with the MCU for development and programming. Control/sense lines: HP_SENSE: Is an acti
17、ve high signal, which indicates if a jack has been plugged into the headphone jack. Spider II Theory of OperationLine 6 confidential. Page 2 of 2 Spider II Theory of OperationLine 6 confidential. Page 3 of 3 GUITAR_SENSE: See Guitar In Section above. -Power Amplifier Section- Analog signal considera
18、tion: Power amp: The +AUDIO_L signal travels to the Power Amplifier PCBA and is input to the Power Amplifier IC U8 at pin 2. The power amp topology is set up as a current feedback system to provide a more tube like response to the user. R51 is used as a current sense resistor and feeds back signal i
19、nto the input. C24 and R52 form an RC network to help suppress oscillation. The ground of the speaker output is connected to the headphone jack so that the speaker is disconnected when headphones are installed. Headphone output and Headphone Sense: R65 and 66 reduce the output of the power amp to a
20、level more suitable for headphones. C44- 46 act as high frequency shunts to chassis ground for EMI. Comparator U10 is needed to sense when headphones are installed because the pin configuration of our jack doesnt work for this application. The reference voltage of U10 is set by R57 and R62. Normally
21、 the voltage at pin 7 is kept lower than pin 6 by the power amp. This keeps the output of the CODEC low. D15 is used to keep negative voltages from damaging U10. Once headphones are installed, pin 4 of J3 is left floating which allows the voltage at pin 7 to rise above pin 6. This causes the output
22、of the comparator to go high and the DSP senses this. The DSP then turns on speaker simulation for the headphones. -Power Supply Section- +3.3V is produced by U11, an adjustable voltage regulator. The output of U11 is determined by the two resistors R63 and R64. D18 provides over-voltage and under-v
23、oltage protection, while C37 provides filtering. +VL is used to supply an optional foot controller on the 3012. +/-HI is provided by the bridge rectifier formed by D16-17,19-20 and filtered by C35 and C36. This voltage feeds the power amp directly. +/-VA are regulated to approx +/-9V by Q1 and Q2. T
24、hese transistors act as discrete regulators because their base is biased by 10V zeners D14 and D13. R54 and R61 provide some level of over current protection. C30 and C34 are used as a time constant in conjunction with R53 and R55 in order to ramp up +/- VA slowly at system start up. This minimizes
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