Aiwa-BZG5-cdm-sm电路图 维修手册.pdf

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1、CD MECHANISM BZG-5 S/M Code No. 09-00C-353-3N8 English SERVICE MANUAL BASIC CD MECHANISM : 3ZG-2E3NM TYPE MVSD3NM MVSD3N1DM MVSD3N8M BASIC CD MECHANISM 3ZG-2E3NM 3ZG-2E3NM 3ZG-2E3NM DATA RadioFans.CN 收音机爱 好者资料库 -2- PROTECTION OF EYES FROM LASER BEAM DURING SERVICING VAROITUS! Laiteen Kyttminen muull

2、a kuin tss kyttohjeessa mainit- ulla tavalla saattaa altistaa kyt-tjn turvallisuusluokan 1 ylit- tvlle nkymttmlle lasersteilylle. VARNING! Om apparaten anvnds p annat stt n vad som specificeras i denna bruksanvising, kan anvndaren utsttas fr osynling laserstrlning, som verskrider grnsen fr laserklas

3、s 1. Caution: Invisible laser radiation when open and interlocks defeated avoid expo- sure to beam. Advarsel:Usynling laserstling ved bning, nr sikkerhedsafbrydere er ude af funktion. Undg udsttelse for strling. CAUTION Use of controls or adjustments or performance of procedures other than those spe

4、cified herein may result in hazardous radiation exposure. ATTENTION Lutilisation de commandes, rglages ou procdures autres que ceux spcifis peut entraner une dangereuse exposition aux radiations. ADVARSEL! Usynlig laserstling ved bning, nr sikkerhedsafbrydereer ude af funktion. Undg udsttelse for st

5、rling. This Compact Disc player is classified as a CLASS 1 LASER product. The CLASS 1 LASER PRODUCT label is located on the rear exterior. This set employs laser. Therefore, be sure to follow carefully the instructions below when servicing. WARNING! WHEN SERVICING, DO NOT APPROACH THE LASER EXIT WIT

6、H THE EYE TOO CLOSELY. IN CASE IT IS NECESSARY TO CONFIRM LASER BEAM EMISSION. BE SURE TO OBSERVE FROM A DISTANCE OF MORE THAN 30cm FROM THE SURFACE OF THE OBJECTIVE LENS ON THE OPTICAL PICK-UP BLOCK. CLASS 1 KLASSE 1 LUOKAN 1 KLASS 1 LASER PRODUCT LASER PRODUKT LASER LAITE LASER APPARAT RadioFans.C

7、N 收音机爱 好者资料库 -3- Precaution to replace Optical block (KSS-213F) 1) After the connection, remove solder shown in the right figure. Body or clothes electrostatic potential could ruin laser diode in the optical block. Be sure ground body and workbench, and use care the clothes do not touch the diode. P

8、ICK-UP ASSY PWB -4- 1) Push down the hooking catch of the CHAS. MECH, and remove the TRAY. 2) Align the arrow mark of the Gear, Main Cam with the black round mark of the CHAS, MECHA as shown below. 3) Confirm that the Slide, Mech Cam is located in the right position, then insert the TRAY gently. Cau

9、tion: If the rotating phase of the Gear, Main Cam is incorrectly adjusted, the chucking operation and tray movement will have malfunction. Align the arrow 2 mark with the black round mark. How to Adjust the Rotating Phase of the Gear, Main Cam -5- UNIT-NAME ! C REF-NO PARTS-NO PARTS-NAME SUFFIX when

10、 GFS is high, this pin outputs a high signal.If GFS is low eight consecutive samples, this pin outputs low. Input when LKIN = 1. (Not connected) Spindle motor servo control output. Disc innermost track detection signal input. 2/3 frequency division output for XTAI pin. (Not connected) Digital power

11、supply. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. Digital GND. Test. Normally, GND. Test. Normally, GND. Center voltage input. Focus error signal input. Sled error signal input. -29- Pin No.Pin NameI/ODescription 41 42

12、 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 IC DESCRIPTION-1/3 (CXD3068Q)-2/2 TE CE RFDC ADIO AVSS0 IGEN AVDD0 ASYO ASYI RFAC AVSS1 CLTV FILO FILI PCO AVDD1 BIAS VCTL V16M VPCO DVDD2 ASYE MD2 DOUT LRCK PCMD BCK EMPH XTSL DVSS2 XT

13、AL1 XTAL0 SOUT SOCK XOLT SQSO SQCK SCSY SBSO EXCK I I I O I O I I I O I O I I I/O O I I O O O O O I I O O O O O I I O I Tracking error signal input. Center servo analog input. RF signal input. Test. No connected. Analog GND. Constant current input for operational amplifier. Analog power supply. EFM

14、full-swing output. (low = Vss, high = VDD) Asymmetry comparator voltage input. EFM signal input. Analog GND. Multiplier VCO1 control voltage input. Master PLL filter output (slave = digital PLL). Master PLL filter input. Master PLL charge pump output. Analog power supply. Asymmetry circuit constant

15、current input. Wide-band EFM PLL VCO2 control voltage input. Wide-band EFM PLL VCO2 oscillation output. Serves as wide-band EFM PLL clock input by switching with the command. (Not connected) Wide-band EFM PLL charge pump output. Digital power supply. Asymmetry circuit on/off (low = off, high = on).

16、Digital Out on/off control (low = off, high = on). Digital Out output. D/A interface. LR clock output. f = Fs D/A interface. Serial data output (twos complement, MSB first). D/A interface. Bit clock output. Outputs a high signal when the playback disc has emphasis, and a lowsignal when there is no e

17、mphasis. (Not connected) Crystal selection input. Low when the crystal is 16.9344MHz; high when it is 33.8688MHz. Digital GND. Crystal oscillation circuit input. When the master clock is input externally, input it from this pin. Crystal oscillation circuit output. Serial data output in servo block.

18、(Not connected) Serial data readout clock output in servo block. (Not connected) Serial data latch output in servo block. (Not connected) Sub-Q 80-bit, PCM peak or level data outputs. CD TEXT data output. SQSO readout clock input. GRSCOR resynchronization input. (Not connected) Sub-Q P to W serial o

19、utput. SBSO readout clock input. -30- 1 2 3 4-12 13-28 29 30 31 32-39 40 41 42 43 44 45-49 50 51 52 53 54 55-62 63 64 65-67 68-79 80 81 82-87 88 89 90 Pin No.Pin NameI/ODescription IC DESCRIPTION-2/3 (ES3880)-1/2 VDD3 _ RAS _ DWE MA0-MA8 DBUS0-DBUS15 _ RESET GND VDD3 YUV0-YUV7 VSYNC HSYNC CPUCLK PCL

20、K2X PCLK AUX0-AUX4 GND VDD3 AUX6 AUX5 AUX7 LD0-LD7 _ LWR _ LOE _ _ LCS3-LCS0 LA0-LA11 GND VDD5 LA12-LA17 ACLK AOUT/SELPLL1 ATCLK O O O I/O I O I/O I/O I I/O I/O I/O I/O I/O I/O I/O O O O O O I/O O I I/O Voltage supply for 3.3 V. DRAM row address strobe. (active low) DRAM write enable. (active low) D

21、RAM multiplexed row and column address bus. DRAM data bus. System reset. (active low) Ground. Voltage supply for 3.3 V. Y is luminance, UV are chrominance data bus for screen video interface. YUV 7: 0 for 8-bit YUV mode. Vertical sync for screen video interface, programmable for rising or falling ed

22、ge. Horizontal sync for screen video interface, programmable for rising or falling edge. RISC and system clock input. CPUCLK is used only if SEL_PLL 1: 0 = 00. Pixel clock; two times the actual pixel clock for screen video interface. Pixel clock qualifier in for screen video interface. Auxiliary con

23、trol pins. (AUX0 and AUX1 are open collectors) Ground. Voltage supply for 3.3 V. Auxiliary control pins. Auxiliary control pins. Auxiliary control pins. RISC interface data bus. RISC interface write enable. (active low) (Not connected) RISC interface output enable. (active low) RISC interface chip s

24、elect. (active low) RISC interface address bus. Ground. Digital supply voltage for 5 V. RISC interface address bus. Master clock for external audio DAC. (8.192 MHz, 11.2896 MHz, 12.288 MHz, 16.9344MHz, and 18.432 MHz) Dual-purpose pin. AOUT is the audio interface serial data output. Pins SEL_PLL 1:

25、0 select phase-lock loop (PLL) clock frequency CPUCLK for the Visba: 00 = bypass PLL. 01 = 54 MHz PLL. 10 = 67.5 MHz PLL. 11 = 81 MHz PLL. Audio transmit bit clock. -31- Pin No.Pin NameI/ODescription IC DESCRIPTION-2/3 (ES3880)-2/2 Dual-purpose pin. ATFS is the audio interface transmit frame sync. P

26、ins SEL_PLL 1: 0 select phase-lock loop (PLL) clock frequency CPUCLK for the Visba. See the SEL_PLL0 pin above for the settings. Dual purpose pin: DRAM output enable. (active low) Audio interface serial data input. Audio receive bit clock. Audio interface receive frame sync. TDM interface serial clo

27、ck. TDM interface serial data receive. TDM interface frame sync. DRAM column address strobe bank 0. (active low) Ground. 91 92 93 94 95 96 97 98 99 100 ATPS/SEL_PLL1 _ DOE AIN ARCLK ARFS TDMCLK TDMDP TDMFS _ CAS GND O I O I I I I I I O -32- 1, 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2

28、3 24 25, 26 27, 28 29-31 32 33 34 35 36 Pin No.Pin NameI/ODescription IC DESCRIPTION-3/3 (ES3889)-1/3 GND NC GND VDD OSC_C AUX0 DSC_D0 AUX1 DSC_S AUX2 DCLK/EXT_CLK _ RST AUX7 MUTE VDD MCLK AUX8 TWS/PLLOUT AUX9 TSD TBCK PWS/SPLL1 RSTOUT GND NC GND VDD RSD/SPLL0 AUX10 AUX11 AUX12 I I I I I/O I/O I/O I

29、 I/O O I I I/O O I I I/O I O I/O I I O I O I I I O I I/O I/O I/O Ground. No connect. Ground. Voltage supply, 5V. Clock for programming to access internal registers. Servo Forward or Control Pin. Data for programming to access internal registers. Servo Reverse or Control Pin. Strobe for programming t

30、o access internal registers. Servo LDON or Control Pin. Dual-purpose pin DCLK is the MPEG decoder clock. EXT_CLK is the external clock EXT_CLK is an input during bypass PLL mode. Video reset. (active low) Servo BRKM/Sense or Control Pin/VFD_DI. Audio mute. (Not connected) Voltage supply, 5V. Audio m

31、aster clock. Servo Mute/Open or Control Pin/VFD_CLK. Dual-purpose pin TWS is the transmit audio frame sync. SPLL_OUT is the select PLL output. Servo SQC0 or Control Pin. Transmit audio data input. Transmit audio bit clock. Dual-purpose pin RWS is the receive audio frame sync. Pins SEL_PLL 1:0 select

32、 the PLL clock frequency for the DCLK output. SEL_PLL1SEL_PLL0DCLK 00Bypass PLL (input mode) 0127MHz (output mode) 1032.4MHz (output mode) 1140.5MHz (output mode) Reset output. (active-low) Ground. No connect. Ground. Voltage supply, 5V. Dual-purpose pin. RSD is the receive audio data input. SEL_PLL

33、0 along with SEL_PLL1 select the PLL clock frequency for the DCLK output. See the table for pin number 23. Servo SQCK or Contrtol pin. 3880 IRQ or Interrupt Output or Control Pin. CD C2PO or Interrupt Input or Control Pin. -33- Pin No.Pin NameI/ODescription 37 38 39 40 41 42 43 44 45, 46 47, 48 49 5

34、0 51 52 53 54 55 56, 57 58 59, 60 61 62, 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 IC DESCRIPTION-3/3 (ES3889)-2/3 PBCK/SER_IN AUX13 AUX14 AUX15 AGND VREFM VREFP AVDD AOR+, AOR AOL, AOL+ MIC2 MIC1 AGND VREF VCM RSET COMP VGND CDAC VVDD YDAC VGND VDAC PLLCAP VDD AUX6 AUX5 AUX4 AUX3 XOUT GND VDD XI

35、N GND NC GND O I I/O I/O I/O I I I I O O I I I I I I I I O I O I O I I I/O I/O I/O I/O O I I I I I Dual-purpose pin. RBCK is the receive audio bit clock. SER_IN is the serial input DSC mode. 0 Parallel DSC mode. 1 Serial DSC mode. Serial Interrupt/CD-Mute or Control Pin. Servo SCOR (SOS1) or Interru

36、pt Input or Control Pin. Interrupt Input or Control Pin. Audio Analog Ground. ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25V. Bypass to analog ground with 47F electrolytic in parallel with 0.1F. DAC and ADC maximum reference. Bypass to VCMR with 10F in parallel with 0.1F.

37、Analog VCC, 5V. Right channel output. Left channel output. Microphone input1. (Not connected) Microphone input2. Audio Analog Ground. Internal resistor divider generates Common Mode Reference (CMR) voltage. Bypass to analog ground with 0.1F. DAC and ADC minimum reference. Bypass to VCMR with 10F in

38、parallel with 0.1F. Full scale DAC current adjustment. Compensation Pin. Video Analog Ground. Modulated chrominance output. (Not connected) Video VCC, 5V. Y Iuminance data bus for screen video port. (Not connected) Video Analog Ground. Composite video output. Audio CAP. Voltage supply, 5V. Servo XLA

39、T or Control Pin / VFD_DO. Servo Data or Control Pin. Servo CCW/Close or Control Pin. (Not connected) Servo CW/Limit or Control Pin. Crystal output. Ground. Voltage supply, 5V. 27MHz crystal input. Ground. No connect. Ground. -34- Pin No.Pin NameI/ODescription 78 79 80 81 82 83 84 85 86-89 90 91 92

40、93 94 95 96 97 98 99 100 IC DESCRIPTION-3/3 (ES3889)-3/3 VDD PCK PCK2 DSC_D1 HSYNC DSC_D2 _ VSYNC DSC_D3 YUV0-3 VDD GND YUV4 DSC_D4 YUV5 DSC_D5 YUV6 DSC_D6 YUV7 DSC_D7 GND I I/O I/O I/O O I/O O I/O I I I I I/O I I/O I I/O I I/O I Voltage supply, 5V. 13.5MHz pixel clock. 27MHz. (2 times pixel clock)

41、Data for programming to access internal registers. Horizontal sync. (active-low) Data for programming to access internal registers. Vertical sync. (active-low) Data for programming to access internal registers. YUV data bus for screen video port. Voltage supply, 5V. Ground. YUV data bus for screen v

42、ideo port. Data for programming to access internal registers. YUV data bus for screen video port. Data for programming to access internal registers. YUV data bus for screen video port. Data for programming to access internal registers. YUV data bus for screen video port. Data for programming to acce

43、ss internal registers. Ground. -35- MECHANICAL EXPLODED VIEW-1/1 A 2 3 4 PWB 3ZG2 5 10 7 8 9 13 11 12 29 17 3 26 22 23 21 20 19 16 14 15 24 18 25 1 6 30 31 31 31 28 CC SH,25-40-0.5 PC a a b b 27 PWB PLATE SHIELD VCD (MVSD3NM,MVSD3N1DM MODEL) (BZA-4) D B -36- UNIT-NAME ! C REF-NO PARTS-NO PARTS-NAME

44、SUFFIX&MODEL != ! SAFTY PARTS C= Components marked All components used on this model at the production line are shown in this service manual. However, please note that not all components will be available as spare parts for after-sales service. Components marked S and O are designated as spare parts

45、 for service and will be stocked at the spare parts centers. Components marked X and R are not designated as spare parts for after sales service, and will not be stocked at the spare parts centers. MECANICAL PARTS LIST -1/1 BZG-5 BZG-5 BZG-5 MVSD3NM MVSD3N1DM MVSD3N8M ELECTRICAL O 1 84-ZG1-672-010 F

46、-CABLE,5P 1.25 210MM WHITE N b c e CD TRANSPORT O 2 84-ZG1-225-010 BELT,SQ1.0-63.3 b c e CD TRANSPORT O 3 84-ZG1-267-010 PULLEY,LOAD MO 8 b c e ELECTRICAL O 4 87-045-364-010 MOT,BCH3B b c e CD TRANSPORT O 5 84-ZG1-238-010 GEAR,WORM N b c e CD TRANSPORT O 6 84-ZG1-248-010 SPR-C,WORM b c e CD TRANSPOR

47、T O 7 8A-ZG1-001-010 TRAY,NO3 BLU b c e CD TRANSPORT O 8 84-ZG1-291-110 HLDR,MAGNET 4 NAT b . . CD TRANSPORT O 8 84-ZG1-291-210 HLDR,MAGNET 4 NAT . . e CD TRANSPORT O 8 84-ZG1-283-110 HLDR,MAGNET V 4 . c . CD TRANSPORT O 9 84-ZG1-259-010 SPR-P,WORM b c e CD TRANSPORT O 10 84-ZG1-239-210 PULLY,WORM N b c e CD TRANSPORT O 11 84-ZG1-224-010 LEVER,TT . c . CD TRANSPORT O 11 84-ZG1-288-010 LEVER,TT NAT b . e CD TRANSPORT O 12 8A-ZG1-002-110 TURN TABLE,NO1 BLU b c