Jvc-KDLX-555-R-Service-Manual 电路图 维修手册.pdf

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1、SERVICE MANUAL COPYRIGHT 2003 VICTOR COMPANY OF JAPAN, LTD. No.49793 2003/5 CD RECEIVER 4979320034 KD-LX555R TABLE OF CONTENTS 1Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2Disas

2、sembly method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3Adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3、 . . . . . . . 28 4Description of major ICs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 S KD-LX555R 1078911 12 STDM SOURCE Area Suffix E - Continental Europe RadioFans.CN 收音机爱 好者资料库 1-32 (No.49793) SECTION 4 Desc

4、ription of major ICs 4.1BA6956AN (IC830, IC831) : Reversible motor driver Block diagram Pin function Truth table TSD CONTROL LOGIC 1 2 3 4 5 6 7 8 9 VREF OUT2 RNF OUT1 VM Vcc FIN GND RIN Pin No. SymbolFunction 1VREFOutput high voltage level control terminal 2OUT2Output terminal for motor 3RNFGND of

5、driver division 4OUT1Output terminal for motor 5VMPower supply for driver division 6VccPower supply for signal division 7FINInput terminal for control logic 8GNDGND 9RINInput terminal for control logic FINRINOUT1OUT2MODE HLHLForward rotation mode LHLHReverse rotation mode HHLLBreak Mode LLOPEN OPENS

6、tand-by mode RadioFans.CN 收音机爱 好者资料库 (No.49793)1-33 4.2BR24C01AFV-W-X (IC1502) : EEPROM Pin layout Block diagram Pin function *1 An open drain output requires a pull-up resister. A0A1A2GND VccWPSCLSDA A0 A1 A2 GND 1 2 3 4 Vcc WP SCL SDA 8 7 6 5 1kbit EEPROM ARRAY 7bit ADDRESS DECODER SLAVE/WORD ADDR

7、ESS REGISTER 7bit 8bit DATA REGISTER CONTROL LOGIC HIGH VOLTAGE GEN.Vcc LEVEL DETECT ACK STARTSTOP Pin nameI/ODescription Vcc-Power supply GND-Ground (0v) A0,A1,A2INSlave address set SCLINSerial clock input SDAIN / OUTSlave and word addressserial data input serial data output *1 WPINWrite protect in

8、put RadioFans.CN 收音机爱 好者资料库 1-34 (No.49793) 4.3BR24C32F (IC703) : EEPROM Pin Layout Pin layout & Block diagram Pin function 4.4HD74HC126FP (IC771) : Changer Control SDASCLWP BR24C32/F VCC GNDA2A1A0 PIN NAMEI/OFunction VCC-Power Supply GND-Ground (0V) A0-A2ISlave Address Set SCLISerial Clock Input SD

9、AI/OSlave and Word Address. Serial Data Input$ Serial Data Output *1 WPIWrite Protect Input 1 2 3 4 8 7 6 5 Vcc WP SCL SDA A0 A1 A2 GND 32 Kbit EEPROM ARRAY 8bit 12bit 12bit DATA REGISTER SLAVE WORD ADDRESS REGISTER ADDRESS DECODER STARTSTOP CONTROL LOGIC VCC LEVEL DETECTHIGH VOLTAGE GEN. ACK 1 2 3

10、4 5 6 7 14 13 12 11 10 9 8 OE1 A1 Y1 OE2 A2 Y2 Vss Vcc OE4 A4 Y4 OE3 A3 Y3 HD74HC126 (No.49793)1-35 4.5BU1923F (IC51) : RDS decoder Pin layout Block diagram 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 QUAL RDATA Vref MUX VDD1 VSS1 VSS3 CMP RCLK N.C. XO XI VDD2 VSS2 T1 T2 - + 8th Switched capacitor filter

11、 PLL 57kHz RDS/ARI PLL 1187.5Hz Bi-phase decoder Differential decoder Measurement circuit Reference clock 100k 100k 120k anti-aliasing filter comparator Analog Power supply Digital Power supply 4 3 5 6 12 11 1314109 78 16 1 2 MUX Vref VDD1 VSS1 VDD2 VSS2 XlX0T1T2 RDATA QUAL RCLK CMPVSS3 1-36 (No.497

12、93) 4.6HA13164A (IC961) : Regulator Terminal layout Block diagram Pin function 123456789 10 11 12 13 14 15 Pin No.SymbolFunction 1EXTOUTOutput voltage is VCC-1 V when M or H level applied to CTRL pin. 2ANTOUTOutput voltage is VCC-1 V when M or H level to CTRL pin and H level to ANT-CTRL. 3ACCINConne

13、cted to ACC. 4VDDOUTRegular 5.7V. 5SW5VOUTOutput voltage is 5V when M or H level applied to CTRL pin. 6COMPOUTOutput for ACC detector. 7ANT CTRLL:ANT output OFF H:ANT output ON 8VCCConnected to VCC. 9BATT DETLow battery detect. 10AUDIO OUTOutput voltage is 9V when M or H level applied to CTRL pin. 1

14、1CTRLL:BIAS OFF M:BIAS ON H:CD ON 12CD OUTOutput voltage is 8V when H level applied to CTRL pin. 13ILM AJAdjustment pin for ILM output voltage. 14ILM OUTOutput voltage is 10V when M or H level applied to CTRL pin. 15GNDConnected to GND. 2 1 11 12 10 1513 14 5 4 6 38 9 7 ILM AJGNDGND C6 10u C5 0.1u C

15、4 0.1u C3 0.1u AUDIO OUT CD OUT CTRL ANT CTRL EXT OUT ANT OUT VCCACC Surge Protector BIASTSD C1 100u C2 0.1u +B ACC BATT.DET OUT COMPOUT VDD OUT SW5VOUT ILMOUT C7 0.1u C8 0.1u R1 UNIT R: C:F note1) TAB (header of IC) connected to GND TAB (No.49793)1-37 4.7 HD74HCT126T-X : (IC1500,IC1503) Buffer Pin

16、arrangement Pin function H : High level L : Low level X : Irrelevant Z : Off (Hhigh-impedance)state of a 3-stage output Block diagram 14 13 12 11 10 9 8 1 2 3 4 5 6 7 Vcc 4C 4A 4Y 3C 3A 3Y 1C 1A 1Y 2C 2A 2Y GND InputOutput CAY LXZ HLL HHH 1Y 2Y 3Y 4Y 1A 1C 2A 2C 3A 3C 4A 4C 1-38 (No.49793) 4.8LA4750

17、5 (IC941) : Power amp. Terminal layout Muting & On Time Control Circuit protective circuit Mute circuit Protective circuit Ripple Filter Stand by Switch 11 16 14 13 25 15 10 4 1 12 22 17 19 18 21 23 24 2 3 5 8 7 9 206 (No.49793)1-39 Terminal layout Pin function AC CONT1 GND1 OUTFR- STBY OUTFR+ Vcc1/

18、2 OUTRR- GND2 OUTRR+ VREF INRR INFR SGND INFL INRL ONTIME OUTRL+ GND3 OUTRL- Vcc3/4 OUTFL+ MUTE OUTFL- GND4 NC Pin No.SymbolFunction 1AC CONT1Header of IC 2GND1Power GND 3OUTFR-Outpur(-) for front Rch 4STBYStand by input 5OUTFR+Output (+) for front Rch 6Vcc1/2Power input 7OUTRR-Output (-) for rear R

19、ch 8GND2Power GND 9OUTRR+Output (+) for rear Rch 10VREFRipple filter 11INRRRear Rch input 12INFRFront Rch input 13SGNDSignal GND 14INFLFront Lch input 15INRLRear Lch input 16ONTIMEPower on time control 17OUTRL+Output (+) for rear Lch 18GND3Power GND 19OUTRL-Output (-) for rear Lch 20Vcc3/4Power inpu

20、t 21OUTFL+Output (+) for front 22MUTEMuting control input 23OUTFL-Output (-) for front 24GND4Power GND 25NCNo connection 1-40 (No.49793) 4.9LA6579H-X (IC1681) : 4-Channel bridge driver Pin layout & Block diagram 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FR FR VIN1 VI

21、N1-B VIN1+B S-GND VIN1-SW MUTE VREFIN VCCS 3.3VREG REGIN VIN2G VIN2 VIN3G VIN3 FR VIN1-A VIN1+A VCCP1 VO+ VO- VO2+ VO2- VO3+ VO3- VO4+ VO4- VCCP2 VIN4 VIN4G FR + - + - + - H L VIN1_SW H: OP-AMP_A L: OP-AMP_B 33k 11k Signal system power supply All outputs ON/OFF H : ON L : OFF MUTE Level shiftLevel s

22、hift Power system GND Signal system power supply 3.3VREG (External:PTP Tr) + - Power system GND Level shift Level shift + - 33k 11k + - + - + - 11k 33k 33k 11k (No.49793)1-41 Pin function Pin No.SymbolFunction 1VIN1-ACH1 input AMP_inverted input 2VIN1+ACH1 input AMP_non-inverted input 3VCCP1CH1 and

23、CH2 power stage power supply 4VO1+Output pin(+)for channel 1 5VO1-CH1 output pin (-) for channel 1 6VO2+Output pin(+)for channel 2 7VO2-Output pin(-)for channel 2 8VO3+Output pin(+)for channel 3 9VO3-Output pin(-)for channel 3 10VO4+Output pin(+)for channel 4 11VO4-Output pin(-)for channel 4 12VCCP2

24、CH3 and CH4 power stage powr supply 13VIN4Input pin for channel 4 14VIN4GInput pin for channel 4(for gain adjustment) 15VIN3Input pin for channel 3 16VIN3GInput pin for channel 3(for gain adjustment) 17VIN2Input pin for channel 2 18VIN2GInput pin for channel 2(for gain adjustment) 19REGINExternal PN

25、P transistor base connection 203.3VREG3.3VREG output pin external PNP transistor,collector connection 21VCCSSignal system GND 22VREFINReference voltage application pin 23MUTEOutput ON/OFF pin 24VIN1_SWCH1 input OP AMP_changeover pin 25S_GNDSignal system GND 26VIN1+BCH1 AMP_B non-inverted input pin 2

26、7VIN1-BCH1 AMP_B inverted input pin 28VIN1CH1 input pin input OP_AMP output pin 1-42 (No.49793) 4.10 M61508FP (IC400) : E.volume Pin layout & Block diagram 18 VDD OUT 1 DATA GND NonFadaer OUT 1 FRONT OUT 1 REAR OUT1 FADER IN 1 TONE OUT 1 TIMER DETECTOR NON FADER VOLUME VOL IN 1 SEL OUT 1 DEFN OUT 1

27、IND 1 INC 1 INB 1 INA 1 DEFN IN 1 DEFP IN 1 REF VOL IN 2 SEL OUT 2 DEFN OUT 2 IND 2 INC 2 INB 2 INA 2 DEFN IN 2 DEFP IN 2 AVDD VDD OUT 2 CLOCK VDD NonFadaer OUT 2 FRONT OUT 2 REAR OUT2 FADER IN 2 TONE OUT 2 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

28、36 NON FADER VOLUME VOLUME 2 LOUDNESS + 3BAND TONE CONTROL (BASS/MID/ TREBLE) LOUDNESS + 3BAND TONE CONTROL (BASS/MID/ TREBLE) VOLUME 1 ZERO CROSS DETECTOR BA - + - + - + + - + - + - + - - + - + AB ZERO CROSS DETECTOR REF 51K 51K 50K 50K 50K 50K 50K 50K 50K 50K 51K 51K 25.5K25.5K 25.5K 30K30K 25.5K

29、VCC SOFT SELECT I/F GNDVDD ZERO DETECT SELECT SWITCH (No.49793)1-43 Pin function Pin No.SymbolFunction 1REFIC signal GND 2DEFP IN 1Ope amp positive input 3DEFN IN 1Ope amp negative input 4INA 1Input selector ch1 input terminal 5INB 1Input selector ch1 input terminal 6INC 1Input selector ch1 input te

30、rminal 7IND 1Input selector ch1 input terminal 8DEFN OUT 1Operation outoutterminal (-) 9SEL OUT 1Input selector output terminal 10VOL IN 1Volume 1 input terminal 11TONE OUT 1Tone output terminal 12FADER IN 1Volume 2 input terminal 13REAR OUT1Fader volume (rear) output terminal 14FRONT OUT 1Fader vol

31、ume (front) output terminal 15NonFadaer OUT 1Non fader volume output terminal 16GNDGND 17DATAControl data input terminal 18VDDOUT 1Connect to GND with capacitor 19VDDOUT 2Connect to GND with capacitor 20CLOCKSerial data clock input terminal 21VDDVDD for digital 22NonFadaer OUT 2Non fader volume outp

32、ut terminal 23FRONT OUT 2Fader volume (front) output terminal 24REAR OUT2Fader volume (rear) output terminal 25FADER IN 2Volume 2 input terminal 26TONE OUT 2Tone output terminal 27VOL IN 2Volume 1 input terminal 28SEL OUT 2Input selector output terminal 29DEFN OUT 2Ope amp output terminal (-) 30IND

33、2Input selector switch ch2 input terminal 31INC 2Input selector switch ch2 input terminal 32INB 2Input selector switch ch2 input terminal 33INA 2Input selector switch ch2 input terminal 34DEFN IN 2Ope amp negative input terminal 35IEFP IN 2Ope amp positive input terminal 36VCCVCC for analog 1-44 (No

34、.49793) 4.11 LC75878W (IC601) : LCD driver Pin layout Block diagram Pin function 1 25 75 51 26 50 100 76 No.SymbolI/OFunction 173SEG1SEG73OSegment driver output pin. 74SEG74 OSegment driver output pin. 75SEG75OSegment driver output pin. 7683COM8COM1OCommon driver output pin. 8487P1P4OGeneral-purpose

35、 output pin. 88VDD-Logic block power supply pin. 89VLCD-LCD driver power supply pin. 90VLCD0OLCD driver bias 4/4 voltage (H-level) power pin. 91VLCD1ILCD driver bias 3/4 voltage (intermediate level) power pin. 92VLCD2ILCD driver bias 2/4 voltage (intermediate level) power pin. 93VLCD3ILCD driver bia

36、s 1/4 voltage (intermediate level) power pin. 94VLCD4ILCD driver bias 0/4 voltage (L-level) power pin. 95VSS-Power supply pin to connect to ground. 96OSCI/OOscillator pin. 97LCD RESETIDisplay off general-purpose output port L fixed input pin. 98CEIChip enable 99CLISynchronization clock 100DIITransfe

37、r data OSC VLCD VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VDD VSS P1 P4 COM1 COM8 S75/COM9 S74/COM10 S73 S1 INH DI CL CE GENERAL PORT COMMON DRIVER SEGMENT DRIVER & LATCH SHIFT REGISTER CONTROL REGISTER CCB INTERFACE CLOCK GENERATOR CONTRAST ADJUSTER (No.49793)1-45 4.12 NJM4565V-X (IC1572) : Dual ope amp Termin

38、al layout & Pin function 4.13 NJU7241F25 (IC1651) : Regulator Pin Layout Block Diagram 4.14 NJU7241F33 (IC1504) : Voltage regulator A - + B - + 8 7 6 5 1 2 3 4 1 2 3 4 5 6 7 8 AOUTPUT A-INPUT A+INPUT V B+INPUT B-INPUT B OUTPUT V GND 1 VIN 2 VOUT 3 5 STB 4 NC Short protect 3 VOUT 1 GND Vref VIN 2 STB

39、 5 GND 1 1 2 3 5 4 PIN FUNCTION 1. GND 2. VIN 3. VOUT 4. NC 5. STB 1-46 (No.49793) 4.15 TA2157FN-X (IC1601):RF amp Terminal layout Block diagram 24 13 1 12 12 11 10 9 8 7 6 5 4 3 2 1 13 14 15 16 17 18 19 20 21 22 23 24 20k 20k 15k 20k 20k 3k 180k 240k 240k 15pF 15pF 40pF 40pF 10pF 60k 60k 22k 22k 94

40、k 94k 14k 50k 20k 20k 20k 40k 50k PEAK 15k 40k 2k 1.75k 1.3V 2k 1k 180k 3k 12k 12k 20k 40k30k10pF 50 A BOTTOM PEAK K 1 x0.5 x2 x0.5 x2 PIN SEL (APC SW) TEB (TE BAL) RFGC (AGC Gian) TEB (TE BAL) VCTRLPIN VCCAPC ON-50%+12dB Normal mode (0dB) HiZAPC ON0%+6dB Normal mode (0dB) GND APC OFF (LDO=H) 50%0dB

41、 CD-RW mode (+12dB) (No.49793)1-47 Pin function Pin No.SymbolI/OFunction 1VCC-3.3V power supply pin 2FNIIMain-beam amp input pin 3FPIIMain-beam amp input pin 4TPIISub-beam amp input pin 5TNIISub-beam amp input pin 6MDIIMonitor photo diode amp input pin 7LDOOLaser diode amp output pin 8SELIAPC circui

42、t ON/OFF control signal, laser diode (LDO) control signal input or bottom/peak detection frequency change pin. 9TEBITracking error balance adjustment signal input pin Adjusts TE signal balance by eliminating carrier component from PWM signal (3-state output, PWM carrier = 88.2kHz) output from TC94A1

43、4F/FA TEBC pin using RC-LPF and inputting DC. TEBC input voltage:GNDVCC 10TENITracking error signal generation amp negative-phase input pin 11TEOOTracking error signal generation amp output pin. Combining TEO signal RFRP signal with TC94A14F/FA configures tracking search system. 12RFDCORF signal pea

44、k detection output pin 13GVSWIAGC/FE/TE amp gain change pin 14VROOReference voltage (VRO) output pin *VRO=1/2VCC When VCC=3.3V 15FEOOFocus error signal generation amp output pin 16FENIFocus error signal generation amp negative-phase input pin 17RFRPOSignal amp output pin for track count Combining RF

45、RP signal and TEO signal with TC94A14F/FA configures tracking search system. 18 19 20 REIS RFGO RFGC I O I RF signal amplitude adjustment amp output pin RF amplitude adjustment control signal input pin Adjusts RF signal amplitude by eliminating carrier component from PWM signal (3-state output, PWM

46、carrier=88.2kHz)output fromTC94A14F/14FA *RFGC pin using RC-LPF and inputting DC. *RFGC input voltage:GNDVCC 21AGCINIRF signal amplitude adjustment amp input pin 22RFOORF signal generation amp output pin 23RFIIRF signal generation amp input pin 24GND-GND pin SEL GND Hiz VCC APC circuit LDO OFFConnec

47、ted VCC through 1k resistor ONControl signal output ONControl signal output VCC GVSWMode GND Hiz CD-RW Normal 1-48 (No.49793) 4.16 TC94A14FA (IC1621) : DSP & DAC Terminal layout & block daiagram Pin function LPF 1-bit DAC Clock generator Micro- controller interface Audio out circuit Digital output A

48、ddress circuit Correction circuit 16 k RAM CLV servo Digital equalizer automatic adjustment circuit Servo control A/D D/A PWM Synchronous guarantee EFM decoder Sub code decoder PLL TMAX VCO Data slicer ROM RAM 49 48474645444342414039383736353433 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 161514

49、13121110123456789 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin No SymbolI/ODescroption 1BCKOBit clock output pin.32fs48fsor 64fs selectable by command. 2LRCKOL/R channel clock output pin.L for L channel and H for R channel. Output polarity can be inverted by command. 3AOUTOAudio data output pin. MSB-first or LSB-first selectable by command. 4DOUTODigital data output pin.Outputs up to double-speed playback. 5IPFOCo