JVC-MXK6-cs-sm 电路图 维修手册.pdf
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1、SP-MXK5SP-MXK5CA-MXK5 PLAY 5V) -Check the main PCB RIC1(L4959) -Check the front PCB UD13(L4959) -Check the main PCB; RBD1(PBL403) RD8(IN5392) -Check the power PCB; Fuse P/T, RFS2, RFS5, RFS6 -Check the main PCB; RR7, RC7, RZD4, RR6 RR5, RR4, RC8, RD3 Check the B+, B- power source RBD1, RBD2, RW2 Che
2、ck the power PCB Fuse, P/T, RFS2, RFS5, RFS6, RFS7, RFS8 Front PCB Does UX1(6MHz) oscllate? Check the main PCB RIC1(L4959) Check the AMP PCB AIC1, AIC2 Check headphone jack soldering condition Check the front PCB UIC( -com), UIC2(M66010gp) Check the AMP PCB AQ2L, 2R, AQ1,2,3,4 Remove it with remocon
3、Is mute selected? Headphone jack short? NoNo No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Replase -com Replase UIC2(M66010) Front PCB When the power is ON H display at pin no.15(UIC2) AQ 2L, 2R, AQ 1,2,3,4 Emitter B+? AMP PCB AIC1, AIC2 pin no. 4,8,9,12 B+,B- nomal? UIC1( -com)pin79 c
4、heck the H? MX-K5/MX-K6 2. Tuner malfunction(FM/AM) 3. Tape malfunction MX-K5/MX-K6 1-28 4. CD MX-K5/MX-K6 L4959 (RIC1) : Voltage regulator 1.Pin layout 2.Block diagram 3.Pin function 5.6V, 250mA REGULATOR REF GEN 8.6V, 600mA REGULATOR SWITCHED 12V, 800mA REGULATOR SWITCHED 12V, 1.3A REGULATOR SWITC
5、HED VS 2/10 GND 6 EN 8V 8 EN 12V(a) 7 EN 12V(b) 5 3 OUT 5.6V 9 OUT 8.6V 11 OUT 12V(a) 1 OUT 12V(b) D97AU569C 1 2 3 4 5 6 7 9 10 11 8 OUT 12V(a) VS OUT 8.6V EN 8.6V EN 12V(a) GND EN 12V(b) N.C. OUT 5.6V VS OUT 12V(b) TAB CONNECTED TO PIN 6D97AU716A PinPinsDescription 1OUT 12V (b)12V/1.3A SWITCHED OUT
6、PUT VOLTAGE 2VSSupply Voltage 3OUT 5.6V5.6V/250mA OUTPUT VOLTAGE 4N.C.not connected 5EN 12V (b)Enable 12V/1.3A SWITCHED OUTPUT VOLTAGE 6GNDGround 7EN 12V (a)Enable 12V/0.8A SWITCHED OUTPUT VOLTAGE 8EN 8.6VEnable 8.6V/0.6A SWITCHED OUTPUT VOLTAGE 9OUT 8.68.6V/0.6A SWITCHED OUTPUT VOLTAGE 10VSSupply V
7、oltage 11OUT 12V (a)12V/0.8A SWITCHED OUTPUT VOLTAGE Description of major ICs MX-K5/MX-K6 1-30 2. BLOCK DIAGRAM 5L9290 (IC201) : 1. Pin layout DIGITAL SIGNAL PROCESSOR FOR CDP DPLL CLV Servo LOCK SMEF SMDP SMDS WDCK EFMI VCO1LF Timing Generator Micom Interface WFCK RFCK C4M XIN ISTAT MLT MDAT MCK MU
8、TE Subcode Out EFM Demodulator ECC 16K SRAM Address Generator SQCK SBCK SOS1 SQDT SBDT Interpolator I/O Interface JITB LPF PWM SADTO LRCKO BCKO LCHOUT RCHOUT VHALF VREF 1-bit DAC Digital Out Digital Filter C2PODATX SADTI LRCKI BCKI S5L9290X DSP+DAC 48-LQFP-0707 VSSA_PLL VCO1LF VSSD_PLL VDDD_PLL XIN
9、XOUT EFMI LOCK SMEF C2PO JITB DATX VDDD3-5V VDDD2-3V SBCK SQDTSMON TESTV SMDS WDCK MUTE BCKI 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 131415161718192021222324 484746454443424140393837 VDDD1_5V VSSD1_5V LKFS LKFS RESETB MLT MDAT MCK ISTAT S0S1 SQCK VSSD2-3V SADTO LRCKO BCKO LRCK
10、I SADTI VSSD_DAC VDDD_DAC RCHOUT VSSA_DAC VREF VHALF VDDA_DAC LRHOUT VDDA_PLL MX-K5/MX-K6 3. Pin function(1/2) NO.NAMEI/OPin Description 1VSSA_PLL-Analog Ground for DPLL 2VCO1LFOPump out for VCO1 3VSSD_PLL-Digital Ground Separated Bulk Bias for DPLL 4VDDD_PLL-Digital Power Separated Bulk Bias for DP
11、LL (3V Power) 5VDDD1-5V-Digital Power (5V Power, I/O PAD) 6XINIXtal oscillator input (16.9344MHz) 7XOUTOXtal oscillator output 8VSSD1-Digital Ground (I/O PAD) 9EFMIIEFM signal input 10LOCKOCLV Servo locking status output 11SMEFOLPF time constant control of the spindle servo error signal 12SMDPOPhase
12、 control output for Spindle Motor drive 13SMDSOSpeed control output for Spindle Motor drive 14WDCKOWord clock output (Normal Speed : 88.2KHz, Double Speed : 176.4KHz) 15TESTVIVarious Data/Clock Input 16LKFSOThe Lock status output of frame sync 17C4MO4.2336MHz clock output 18RESETBISystem Reset at L
13、19MLTILatch signal input from Micom 20MDATISerial data input from Micom 21MCKISerial data receiving clock input from Micom 22ISTATOThe internal status output to Micom 23S0S1OSubcode sync signal(S0+S1) output 24SQCKISubcode-Q data transfering bit clock input MX-K5/MX-K6 1-32 3. Pin function (2/2) NO.
14、NAMEI/OFunction Description 25SQDTOSubcode-Q data serial output 26MUTEISystem mute at H 27VDDD2-3V-Digital Power (3V Power, Internal Logic) 28VSSD2-Digital Ground (Internal Logic) 28VDDD3-5V-Digital Power (5V Power, I/O PAD) 30SBCKISubcode data transfering bit clock 31JITBOInternal SRAM jitter margi
15、n status output 32C2POOC2 pointer output 33DATXODigital audio data output 34SADTOOSerial audio data output (48 slot, MSB first) 35LRCKOOChannel clock output 36BCKOOBit clock output 37BCKIIBit clock input 38LRCKIIChannel clock input 39SADTIISerial audio data input (48 slot, MSB first) 40VSSD_DAC-Digi
16、tal Ground for DAC 41VDDD_DAC-Digital Power for DAC (3V Power) 42RCHOUTORight-Channel audio output through DAC 43VSSA_DAC-Analog Ground for DAC 44VREFOReferance Voltage output for bypass 45VHALFOReferance Voltage output for bypass 46VDDA_DAC-Analog Power for DAC (3V Power) 47LCHOUTOLeft-Channel audi
17、o output through DAC 48VDDA_PLL-Analog Power for PLL (3V Power) MX-K5/MX-K6 BA3837 1.Block diagram 161514131211109 12345678 LOGIC SW2 SW1 R L + R L R L + + + + + + + + VCCMICLOUTFKTKLINBIASGND CBAROUTLPLPLPRIN BA4560 (AIC3, AIC4, AIC5, AIC6, AIC7, FIC4, HIC1, JIC2) : OP amp. 1.Pin layout + + 1 2 3 4
18、 8 7 6 5 OUT1 IN1 + IN1 VEE VCC OUT2 IN2 + IN2 1ch 2ch KA9258D (IC925) : 4-ch Motor driver 2827262524232221201918171615 1234567891011121314 GND GND 10K REGULATOR 10K 10K VCCVCC 10K 10K T S D 10K 10K 10K 50K MUTE +- LEVEL SHIFT -+ LEVEL SHIFT MX-K5/MX-K6 1-34 RF AMP & SERVO SIGNAL PROCESSOR 2. BLOCK
19、DIAGRAM 4 12 RF AGC & EQ Control Focus OK Detect Defect Detect Mirror Gen Center Voltage APC. Laser Control & LPC Tracking Servo Loop - Gain & Phase Compensation - Track Jump - Offset Adjust - TZC Gen. Tracking Error (RW) I/V AMP RF & Focus Error (CD-RW) I/V AMP Hardware Logic - Auto-Sequencer - Fas
20、t Search - Febias, Focus Servo, Tracking Offset ADJ. - Tracking Balance & Gain Adjust - Interruption Detect - EFM Muting System Sled Servo & Kick Gen Spindle Servo LPF EFM Comparator Micom Data Interface Logic Decoder Focus Servo Loop - Gain & Phase Compensation - Focus Search - Offset Adjust - FZC
21、Gen. EQO PD LD LPFT TEIO TZC& SSTOP ATSC TEO TEM SLP SLO SLM FEO FEM SPDLO SPDLM EQI RFO RFM EQC VREF PDE PDF PDBD PDAC ISTAT MCK MDATA MLT RESET WDCK CLVI LOCK ASY EFM 5 45 46 44 43 6 7 8 9 10 11 14131516171918202221 24 23 30 29 25 26 27 28 29 36 33 34 35 37 38 39 4140424748123 EFMI DCCI DCC0 MCP D
22、CB VCC/ VDD FRSH FSET FLB FGD FSI TGU S1L9226X TEO TEM SLP SLO SLM ISTAT MCK MDATA MLT RESET WDCK CLVI LOCK ASY EFM SPM EFMI VCC FRSH FSET FLB FGD FSI TGU EQO EQI RFO RFM PD LD37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 123456789101112 363534333231302928272625 SPO FEM FEO
23、 GND TZC/SSTOP TEIO LPFT ATSC PDAC PDF PDBD PDE DCB MCP DCCI DCCO VREF EQC KB9226 (IC101) : 1. Pin layout MX-K5/MX-K6 Pin No. SymbolI/ODescription 1RFMIRF summing amp. inverting input 2RFOORF summing amp. output 3EQIIRFO DC eliminating input(use by MIRROR, FOK ,AGC & EQ terminal) 4EQOORF equalizer o
24、utput 5EFMIIEFM slice input. (input impedance 47K) 6VCCPMain power supply 7FRSHICapcitor connection to focus search 8FSETIFilter bias for focus,tracking,spindle 9FLBICapacitor connection to make focus loop rising band 10FGDITerminal to change the hign frequency gain of focus loop 11FSIIFocus servo i
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