Jvc-KDLX-333-R-Service-Manual 电路图 维修手册.pdf

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1、SERVICE MANUAL CD RECEIVER No.49715 Jun. 2002 COPYRIGHT 2002 VICTOR COMPANY OF JAPAN, LTD. KD-LX333R KD-LX333R Area Suffix E EX Continental Europe Central Europe Contents Safety precaution Preventing static electricity Disassembly method Adjustment method 1-2 1-3 1-4 1-13 1-14 1-16 1-16 1-1733 Flow

2、of finctional operation intil opelation until TOC read Maintenance of laser pickup Replacement of laser pickup Description of Major ICs KD-LX333R 1078911 12 OFF STDM ATT SOURCE RadioFans.CN 收音机爱 好者资料库 KD-LX333R 1-17 Description of major ICs Micro- controller interface Audio output circuit Digital ou

3、tput 16k RAM Address circuit 1-bit DACServo control Clock generator LPF PWM D/A A/D ROM CLV servo Sync signal protection EFM Sub code detector Data slicer VCO PLL TMAX Digital equalizer automatic adjustment circuit RAM Correction circuit 48474645444342414039383736353433 12345678910111213141516 17 18

4、 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 BCK LRCK AOUT DOUT IPF VDD3 VSS3 SBOK CLCK DATA SFSY SBSY /HSO /UHSO PVDD3 PDO VXDD3 XO XI XVSS3 TEIN VDD3 VSS3 DMO FMO AVDD3 SEL TEBC RFGC VREF TRO FOO DVSS3 RO DVDD3 DVR LO DVSS3 ZDET VSS5 BUS0 BUS1 BUS2 BUS

5、3 BUCK /CCE /RST VDD5 TEZI TEI SBAD FEI RFRP RFZI RFCT AVDD3 RFI SLCO AVSS3 VCOF RVREF LPFO LPFN TMAX TC9490FA (IC521) : DSP & DAC 1.Pin layout & Block daiagram RadioFans.CN 收音机爱 好者资料库 KD-LX333R 1-18 2.Pin function (1/2) I/O O O O O O - - O I/O O O O O O - O O I O - O - O I - I I I I I I I O O - Fun

6、ction Bit clock outputpin 32fs, 48fs, or 64fs selectable by command. L/R channel clock output pin.L for L channe and H for R channel. Output polarity can be inverted by command. Audio data output pin. MSB-first or LSB-first selectable by command. Digital data output pin. Outputs up to double-speed p

7、layback. Correction flag output pin.When set to H,AOUT output cannot be corrected by C2 correction processing. Digital 3.3V power supply voltage pin. Digital GND pin. Subcode Q data CRCC result output pin.H level when result is OK. Subcode P-W data read clockI/O pin. I/O polarity selectable by comma

8、nd. Subcode P-W data output pin. Playback frame sync signal output pin. Subcode block sync signal output pin. H level at S1 when subcode sync is detected. Playback speed mode flag output pins. PLL-only 3.3V power supply voltage pin. EFM and PLCK phase difference signal output pin. TMAX detection res

9、ult output pin. Inverted input pin for PLL LPF amp. Output oin for PLL LPF amp. PLL-only VREF pin. VCO filter pin. Analog GND pin. DAC output pin for data slice level generation. RF signal input pin.Zin selectable by command. Analog 3.3V power supply voltage pin. RFRP signal center level input pin.

10、RFRP signal zero-cross input pin. RF ripple signal input pin. Focus error signal input pin. Sub-beam adder signal input pin. Tracking error input pin. Inputs when tracking servo is on. Tracking error signal zero-cross input pin. Focus equalizer output pin. Tracking equalizer output pin. Analog refer

11、ence power supply voltage pin. Symbol BCK LRCK AOUT DOUT IPF VDD3 VSS3 SBOK CLCK DATA SFSY SBSY /HSO /UHSO PVDD3 PDO TMAX LPFN LPFO PVREF VCOF AVSS3 SLCO RFI AV RFCT RFZI RFRP FEI SBAD TEI TEZI FOO TRO VREF Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 3

12、2 33 34 35 TC9490FA(2/3) Playback speed/UHSO/HSO H H L - H L L - Normal Double 4 times - TMAX OutputTMAX Detection result Longer than fixed period Within fixed period Shorter than fixed period PVDD3 HIZ AVSS3 RadioFans.CN 收音机爱 好者资料库 KD-LX333R 1-19 2.Pin function (2/2) I/O O O O - O O - - I - I O - -

13、 O - - O - O - I/O I I I - Function RF amplitude adjustment control signal output pin. Tracking balance control signal output pin. APC circuit ON/OFF signal output pin. At laser on,high impedance with UHS=L ,H output with UHS=H. Analog 3.3V power supply voltage pin. Feed equalizer output pin. Disc e

14、qualizer output pin. Digital GND pin. Digital 3.3V power supply voltage pin. Test input pin. Normally,fixed to L. System clock oscillator GND pin. System clock oscilatoe input pin. System clock oscillator output pin. System clock oscillator 3.3V power supply voltage pin. DA converter GND pin. R-chan

15、nel data forward output pin. DA converter 3.3V power supply pin. Reference voltage pin. L-channel data forward output pin. DA converter GND pin. 1 bit DA converter zero data detection flag output pin. Microcontroller interface GND pin. Microcontroller interface data I/O pins. Microcontroller interfa

16、ce clock input pin. Microcontroller interface chip enable signal input pin.At L. Bus0 to BUS3 are active. Reset signal input pin. At reset,L. Microcontroller interface 5V power supply pin. Symbol RFGC TEBC SEL AVDD3 FMO DMO VSS3 VDD3 TESIN XVSS3 XI XO XVDD3 DVSS3 RO DVDD3 DVR LO DVSS3 ZDET VSS5 BUS0

17、 BUS1 BUS2 BUS3 BUCK /CCE /RST VDD5 Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TC9490FA(3/3) 8 7 6 54 3 2 1V+ B OUTPUT B INPUT B INPUT A INPUT A INPUT A OUTPUT - V- + + - NJM4565MD (IC151,IC171,IC323) : Operational amp KD-LX333R 1-20 20k 20k 20k 20

18、k 20k 180k 60k 15pF 1 k x0.5 x0.5 1.75k 240k 15pF 14k2k 1k 2k 50k x2 x2 240k 60k 80k 80k 20k 20k 180k 40pF 40pF 3k 3k 12k 12k 15k 50 A 10pF 20 A 40k 20k 20k 20k 50k PEAK 15k 10pF 40k 60 A 1.3V BOTTOM PEAK 40k 30k 13GVSW VRO FEO FEN RFRP RFRPIN RFGO RFGC AGCIN RFO RFN GND 14 15 16 17 18 19 20 21 22 2

19、3 24 12RFDC TEO TEN TEBC SEL LDO MDI TNI TPI FPI FNI Vcc 11 10 9 8 7 6 5 4 3 2 1 TA2147F-X (IC501) : RF amp. 1.Terminal layout 2.Block diagram KD-LX333R 1-21 3.Pin function I/O - I I I I I O I I I O O I O O I O I O I I O I - Function 3.3V Power supply pin Main-beam amp input pin Main-beam amp input

20、pin Sub-beam amp input pin Sub-beam input pin Monitor photo diode amp input pin Laser diode amp output pin APC circuit ON/OFF control signal,laser diode (LDO) control signal input or bottom/peak detection frequency change pin. Tracking error balance adjustment signal pin Adjusts TE signal balance by

21、 eliminating carrier component from PWM signal(3-state output, PWM carrier = 88.2kHz) output from TC9490F/FA TEBC pin using RC-LPF and inputting DC. TEBC input voltage:GNDVcc Tracking error signal generation amp negative-phase input pin Tracking error signal generation amp output pin. Combining TEO

22、signal and RFRP signal with TC9490F/FA configures tracking search system. RF signal peak detection output pin AGC/FE/TE amp gain change pin Reference voltage (VRO) output pin *VRO = 1/2 Vcc when Vcc = 3.3V Focus error signal generation amp output pin Focus error signal generation amp negative-phase

23、input pin Signal amp output pin for track count Combining RFRP signal TEO signal with TC9490F/FA configures tracking search system. Signal generation amp input pin for track count RF signal amplitude adjustment amp output pin RF amplitude adjustment control signal input pin Adjusts RF signal amplitu

24、de by eliminating carrier component from PWM signal (3-state output, PWM carrier = 88.2kHz) output from TC9490F/FA RFGC pin using RC-LPF and inputting DC. *RFGC input voltage : GND-Vcc RF signal amplitude adjustment amp input pin RF signal generation amp output pin RF signal generation amp input pin

25、 GND pin Symbol Vcc FNI FPI TPI TNI MDI LDO SEL TEBC TEN TEO RFDC GVSW VRO FEO FEN RFRP RFRPIN RFGO RFGC AGCIN RFO RFN GND Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 LDOSEL GNDOFF HIZ Vcc ON ON Connected to Vcc through 1k resistor Control signal output Control signal outp

26、ut APC circuit ModeGVSW GND HIZ Vcc CD-RW CD-DA CD-DA KD-LX333R 1-22 TA8273H (IC941) : Power amp 11 620 1 4 10 15 25 13 14 16 12 9 8 5 7 2 22 17 19 18 21 23 24 3 - + - + - + - + - + - + - + - +INRF INRR ST BY Vcc 1/2Vcc 3/4 OUT RF+ OUT RF- GND OUTRR+ OUTRR- GND REF INLF INLR PRE GND ON TIME Muting &

27、 ON Time Control Circuit Protective circuit Protective circuit Mute circuit Ripple Filter Stand by Switch AC CONT2 + + 0.22 F 2200 F0.022 F 0.22 F AC CONT1 +5V ST ON + + + + 47 F 0.22 F 0.22 F 22 F + Mute 10K + 3.3 F OUTLF+ OUTLF- Low Level Mute ON GND OUTLR+ OUT LR- GND 1.Block diagram KD-LX333R 1-

28、23 2.Terminal layout 3.Pin function TA8273H AC CONT 1 GND OUTRR- STBY OUTRR+ VCC1/2 OUTRF- GND OUTRF+ REF INRF INRR PREGND INLR INLF ONTIME OUTLF+ GND OUTLF- VCC3/4 OUTLR+ MUTE OUTLR- GND AC CONT 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SymbolPin No.Function Header of IC P

29、ower GND Outpur(-) for Rear Rch Stand by input Output (+) for Rear Rch Power input Output (-) for Front Rch Power GND Output (+) for Front Rch Ripple filter Front Rch input Rear Rch input Signal GND Rear Lch input Front Lch input Power on time control Output (+) for Front Lch Power GND Output (-) fo

30、r Front Lch Power input Output (+) for Rear Lch Muting control input Output (-) for Rear Lch Power GND Header of IC KD-LX333R 1-24 UPD784217AGC168 (IC701) : Main micon 1.Pin layout 2.Pin functions(1/3) 1 25 75 51 100 76 26 50 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

31、26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 I/O I I I I O O O O - - - - - - I I I I I I I I - - I I I I I I I I - O O - I O I/O I O O Function CD mechanical switch 2 detection signal input CD mechanical switch 3 detection signal input CD mechanical switch 4 detection signal input Rest switch

32、detection signal input Motor signal control signal output at loading Motor signal control signal output at leject DIMMER pulse control output POWER ON:H,FLAT PANEL:L 5V GND Reset detection teaminal CD mechanical switch 1 detection signal input J-BUS int POWER SAVE2. Operating together with BACKUP.H

33、input:STOP Pulse signal for CRUISE input(only in 330R) RDS clock input RDS data input Remocon input(111R:READY) 5V 5V Temperature detection input Key input 0 Key input 1 Key input 2 Level meter input MRC output voltage detection S.QUALITY level input S.METER level input GND Subwoofer volume control

34、analog output Dot matrix contrast adjustment analog output 5V J-BUS data input J-BUS data output J-BUS clock input and output H:LX333R L:LX111R Data output to LCD driver Clock output to LCD driver Symbol SW2 SW3 SW4 RST-SW LMO LM1 DIM-OUT ILLUM1 VDD X2 X1 VSS XT2 XT1 RESET SW1 BUS-INT PS2 CRUISE RDS

35、-SCK RDS DA REMOCON AVDD AVREFO TEM1 KEY0 KEY1 KEY2 LEVEL MRC SQ SM AVSS W-VOL DOT-CNT AVREF BUS-SI BUS-SO BUS-SCK STAGE2 LCD-DA LCD-SCK KD-LX333R 1-25 2.Pin functions(2/3) Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

36、 83 84 85 86 87 88 89 90 91 92 93 94 I/O O O I O O O O O O O I O O I I I I I I I O O - O O O I I O - I I O O O O O O - O O O O O - O O - O O O - Function Chip enable output 1 to LCD driver Buzzer output 12C communication data input 12C communication data output 12C communication clock output J-BUSI/

37、O signal terminal Tray motor negative signal output terminal Tray motor positive signal output terminal Motor control signal output in door down Motor control signal output in door up Stereo signal input L:Stereo AF check output AF check:L Chameleon machanical switch 1 detection signal input Chamele

38、on machanical switch 2 detection signal input Chameleon machanical switch 3 detection signal input Chameleon machanical switch 4 detection signal input Chameleon machanical switch 5 detection signal input Rotary volume signal 1 input Rotary volume signal 2 input Auto seek/stop selection output SEEK:

39、L STOP:H FM/AM selection output FM:H AM:L IC control CE output IC control data output IC control clock output IC control data input Telephone mute detection input POWER AMP ON/OFF selection output GND Dimmer detection input L:dimmer ON Power save 1 Operating together with ACC.Power save :L Operating

40、 :H Power ON/OFF selection output Power ON:H CD power supply control signal output CD:H Mute output MUTEON:L Subwoofer cut off frequency control output 1 Subwoofer cut off frequency control output 2 Subwoofer mute output MUTE ON:H 5V data output terminal clock signal output terminal FM band filter s

41、election signal output CD-DA/CD-RW selection control output CD-RW:L Reset signal output to LCD driver Door motor kick signal output Tray motor kick signal output Data cmmunication clock output with CDLSI Data cmmunication clock CE with CDLSI CDLSI reset signal output GND Symbol LCD-CE1 BUZZER 12C-DA

42、I 12C-DAO 12C-CLK BUS-I/O TMO TM1 DMO DM1 ST NC AFCK C-SW1 C-SW2 C-SW3 C-SW4 C-SW5 VOL1 VOL2 SEEK/STP NC FM/AM PLL-CE PLL-DO PLL-CLK PLL-DI TEL-MUTE AMP-KILL VSS DIM -IN PS1 POWER CD-ON MUTE W-LPF1 W-LPF2 W-MUTE VDD VOL-DA VOL-CLK CF-SEL GVSW LCD RST NC DMK TMK NC BUCK CCE RST TEST KD-LX333R 1-26 2.

43、Pin functions(3/3) Pin No. 95 96 97 98 99 100 I/O I/O I/O I/O I/O I O Function Data communication input and output port 0 with CDLSI Data communication input and output port 1 with CDLSI Data communication input and output port 2 with CDLSI Data communication input and output port 3 with CDLSI H:not

44、 for 8cm DISC L:for 8cm DISC Symbol BUSO BUS1 BUS2 BUS3 DISCSEL NC +- + - - + +- - - + + REFR REFL FILTER 8910 111213 14 1234567 INRNFRFILNFLCL+ Vcc INL CL-LGNDOUTLOUTRRGNDCR- CR+ 17 8 3220 14 BA3220FV-X (IC301,IC401) : Line out amp 1.Pin layout 2.Block diagram KD-LX333R 1-27 BD3860K (IC911) : E.Vol

45、 & Loud 1.Terminal layout 2.Block diagram 3.Pin function 1 11 33 23 34 44 22 12 13 12 7 8 37 10 11 41 42 43 44 1 2 3 4 65940363534332832313029191514 39383725242623222120181716 GNDFIL VCCSEL1 0 18 dB 0 18 dB VIN1LOUD1HF1LF1 DET1TIN1 TNF1BNF1 OUTF1 OUTR1 SI SC OUTR2 OUTF2 BOUT2BNF2TNF2TIN2BBOUT2MIX2VC

46、A2DET2LF2HF2LOUD2VIN2SEL2 D2 C2 B2 A2 D1 C1 B1 A1 BOUT1VCA1MIX1 BBOUT1 POWER SUPPLY INPUT GAIN INPUT GAIN MAIN VOLUME 0 -40 dB LOUDNESS MAIN VOLUME 0 -40 dB LOUDNESS LOW(f=50Hz) 6dB PROCESS CONTROL +3 to 12dB (f=10kHz) LOW(f=50Hz) 6dB PROCESS CONTROL +3 to 12dB (f=10kHz) TREBLE -14 +14dB TREBLE -14

47、+14dB BASS -14 +14dB BASS -14 +14dB FADER CH1 FRONT 0 -5 dB FADER CH2 FRONT 0 -5 dB FADER CH1 REAR 0 -5 dB FADER CH2 REAR 0 -5 dB LOGIC INPUT SELECTOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CH2 Input Pin A CH2 Input Pin B CH2 Input Pin C CH2 Input Pin D 1/2 VCC Pin Ground Pin Seria

48、l Data Receiving Pin Serial Clock Receiving Pin Power Supply Pin CH2 Rear Output Pin CH2 Front Output Pin CH1 Rear Output Pin CH1 Front Output Pin CH1 Bass Filter Setting Pin CH1 Bass Filter Setting Pin CH2 Bass Filter Setting Pin CH2 Bass Filter Setting Pin CH2 Treble Filter Setting Pin CH1 Treble

49、Filter Setting Pin CH2 Treble Input Pin CH2 BBE II Signal Output Pin CH2 Output MIX Amplifier Inverse Input Pin A2 B2 C2 D2 FIL GND SI SC VCC OUTR2 OUTF2 OUTR1 OUTF1 BOUT1 BNF1 BOUT2 BNF2 TNF2 TNF1 TIN2 BBOUT2 MIX2 Pin No. SymbolFunction 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 CH2 High Pass VCA Output Pin CH2 Low Pass Filter Setting Pin CH2 High Pass Filter Setting Pin CH2 High Pass Attack/Release Time Setting P