Kenwood-KD-CMP-8017-Service-Manual 电路图 维修手册.pdf

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1、 2001-3 PRINTED IN JAPAN B51-7755-00 (N) 3386 CD RECEIVER KDC-MP6090R/MP7018 KDC-MP8017 SERVICE MANUAL 47W 4X KDC-MP8017 DAB 47W 4X KDC-MP7018 DAB 47W 4X KDC-MP6090R DAB PTY TI VOL ADJ K3i KDC-MP8017 KDC-MP7018KDC-MP6090R ESCUTCHEON ASSY (B07-3007-03) PANEL ASSY (A64-2267-02) PANEL ASSY (A64-2266-02

2、) ESCUTCHEON ASSY (B07-3007-03) DC CORD (E30-4940-05) : KDC-MP8017 DC CORD (E30-4939-05) : KDC-MP7018 ANTENNA ADAPTOR (T90-0523/0534-05) : KDC-MP6090R BATTERY (SIZE: AAA) Not supplied as service parts SCREW SET (N99-1704-05) SCREW SET (N99-1700-05) : KDC-MP8017 KDC-MP7018 STAY (J54-0606-04) : KDC-MP

3、8017 KDC-MP7018 LEVERx2 (D10-4562-04) ESCUTCHEON (B07-3010-02) : KDC-MP8017 KDC-MP7018 REMOTE CONTROLLER ASSY (A70-0883-05) : KDC-MP7018 MOUNTING HARDWARE ASSY (J21-9641-13) PLASTIC CABINET ASSY (A02-1497-03) ESCUTCHEON ASSY (B07-3007-03) FRONT GLASS (B10-4033-01) FRONT GLASS (B10-4034-01) FRONT GLA

4、SS (B10-4035-01) PANEL ASSY (A64-2268-02) DC CORD (E30-4943-05) : KDC-MP6090R The MECHANISM OPERATION DESCRIPTION is the same as model KDC-S3007 and KDC-5050RG. Please refer to the service manual for model KDC-S3007(B51-7029-00) or KDC-5050RG(B51-7099-00). RadioFans.CN 收音机爱 好者资料库 KDC-MP6090R/MP7018/

5、MP8017 2 BLOCK DIAGRAM DMX-1760 BLOCK DIAGRAM ANALOG OUT COMMUNICATION TO HOST IC2 CONTROL IC3 CONTROL MP3 BIT CONTROL MP3 TIME DISPLAY CD TEXT CONTROL FILE ANALISIS (ISO9660) IIS DATA SERVO CONTROL EFM DECODE ROM DECODE ATAPII/F (NOT USED) MP3 DECODE IC2 IC11 DPU1 CD PICK UP IC10 IC1 IC6 IC3IC9,12

6、IC5 RF AMP (4Mbit) D-RAM MUX LPF DAC CD-ROM DECODER SERVO CONTROLER MECHA CONTROL COMPUTER 4cH BTL DRIVE MPEG 2.5 LAYER III AUDIO DECODER IIC MPEG RadioFans.CN 收音机爱 好者资料库 KDC-MP6090R/MP7018/MP8017 3 BLOCK DIAGRAM PLL+B FM+B Q45,47 Q46,48 AM+B DIMMER MUTE 2WAY DET. ACC BU DET. A8VA8V IC10 Q14-16 Q19-

7、22 IC8 SERVO AVR IC11 Q17 SERVO+B SW5V Q13 Q55,56 Q33 Q11,12 SW5V BU5V BU5V P CON ANT-CON Q28,31 Q27,29 Q30,32 MUTE IC3 Q7 DRIVER MUTE Q1,2,5,6 POWER IC IC4 u-COM CD CH F/E A1 E-VOL IC2 PRE OUT SP-OUT DIMMER TEL-MUTE ACC ANT-CONT P-CONT ANT-CONT P-CONT DECODER RDS (E)TYPE IC1 IC7 Q52 EX.AMP CONTROL

8、ILLUM +B BUFFER NOISE Q51 PRE OUT OUTPUT VOLTAGE CONTROL EX.AMP Q25 Q26 Q34 (M,E) TYPE (E) TYPE (E) TYPE (K,M) TYPE NAVI-MUTE PANEL 5V PANEL 5V PANEL POSITION DET. CH QUAL SERVO+B MUTE R STOP SW2 LO/EJ MUTE L RST SW3 SW1 SDA SCL A8V BU5V SW5V RST REQ C CLK CH-CON DATA H REQ H CD AM FM P MUTE MUTE SW

9、5V PANEL5V ILL+B SRT-SW1 SRT-SW2 P ON SERVO+B RDCK RDDA QUAL SDA SCL AFSAFS A8V PLL DATA PLL CLK IFC OUT S-METER SW5V DATA C BACK UP BU5V 600mV 3600mVCHANGER AM 1800mVFM 230mV 1200mV 1200mV 251mV (E TYPE) 470mV (K,M TYPE) AUDIO OUT FM+B NOISE 3600mVCD K,M TYPEMODEL 3600mV 3600mV 855mV 1372mV E TYPE

10、MO SW RESET IC MATRIX KEY L DATAL L CE L CLK/PANEL DIMMER REMO RESET DRIVER MUTE LCD DRIVER IC1 IC2 Q5 Q3,4 ED1 SW RESET LCD (BACK LIGHT WLED) DIMMER PWM CONTROL REMO G/R SW LCD AVR PANEL 5V (X13- ) MSW5VMSW5V IC12 MSW5V RadioFans.CN 收音机爱 好者资料库 KDC-MP6090R/MP7018/MP8017 4 COMPONENTS DESCRIPTION Ref.

11、No.Component NameApplication/FunctionOperation/Condition/Compatibility IC1LC75808WLCD driver with the key matrix IC2RS-171Remote sensor IC Q1DTA114EUA or KRA302Key-permission SWFor the key scanning start Q32SD2114KRed LED SWWhen a base goes Hi, RED LEDs are turned on. Q42SD2114KGreen LED SWWhen a ba

12、se goes Hi, GREEN LEDs are turned on. Q52SC2412K or 2SD601AVLCD AVR Q6DTA114EUA or KRA302REMO SW While a base goes Lo, PAN 5V is supplied to the Remote sensor IC. Q7DTC143ZKDimmer SW Usually Q7s base goes Hi. When DIMMER mode is selected, pulse wave shape is applied to Q7s base. Ref.No.Component Nam

13、eApplication/FunctionOperation/Condition/Compatibility IC1UPD703033GC057System MI-COM. IC2TDA7407DE.VOL in Multimedia mode SRC_INT must be connected to VDD. In Functional mode TESTEN must be connected to VDD, SCANEN to ground. 12 KDC-MP6090R/MP7018/MP8017 CIRCUIT DESCRIPTION (MP3) I FUNCTIONAL DESCR

14、IPTION G Clock Signal The STA013 input clock is derivated from an external source or from a industry standard crystal oscillator, generating input frequencies of 10, 14.31818 or 14.7456MHz. Note Z919 : 10MHz XTI is an input Pad with specific levels SymbolParameterTest ConditionMin.Typ.Max.Unit VIL L

15、ow Level VDD1.8V Input Voltage VIH Hight Level VDD0.8V Input Voltage CMOS compatibility The XTI pad low and hight levels are CMOS compatible; XTI pad noise maegin is better than typical CMOS pads. TTL compatibility The XTI pad low level is compatible with TTL while the hight level is not compatible

16、(for example if VDD = 3V TTL min hight level = 2.0V while XTI min hight level = 2.2V) G Serial Input Interface STA013 receives the input data (MSB first) thought the Serial input Interface (Fig. 2). It is a sirial communication interface connected to the SDI (Serial Data Input) and SCKR (Receiver Se

17、rial Clock). The interface can be configured to receive data sampled on both rising and falling edge of the SCKR clock. The BIT_EN pin, when set to low, forces the bitstream input interface to ignore the incoming data. For proper operation BIT_EN line shold be toggled only when SCR is stable low (fo

18、r both SCLK_POL configuration) The possible configurations are described in Fig. 3. G PLL & Clock Generator System When STA013 receives the input clock, as described in “Clock Signal”, and a valid layer # input bit stream, the internal PLL locks, providing to the DSP Core the master clock (DCLK), an

19、d to the Audio Output Interface the nomi- nal frequencies of the incoming compressed bit stream. The STA013 PLL block diagram is described in Figure 4. The audio sample rates are obtained diving the oversam- pling clock (OCLK) by software programmable factors. The operation is done by STA013 embedde

20、d software and it is transparent to the user. The STA013 PLL can drive directly most of the commercial DACs families, providing the VCO frequency with a soft- ware programmable dividers. DATA SOURCE MPEG DECODER SERIAL AUDIO INTERFACE RXTX PLLIIC IIC FILT P SDA SCL XTI XTO DATA_REQ SDI SCKR BIT_EN S

21、DO SCKT LRCKT DAC OCLK DATA IGNORED DATA IGNORED DATA VAOLID SDI SCKR SCKR BIT_EN SCLK_POL=0 SCLK_POL=4 Switching Circuit PFDCP MVCO X S N XTI2OCLK XTI2DSPCLK FRAC Update FRAC Disable PLL XTI CC R OCLK DCLK Fig. 2 MPEG Decoder Interfaces Fig. 3 Serial Input Interface Clocks Fig. 4 PLL and Clock Gene

22、ration System KDC-MP6090R/MP7018/MP8017 13 CIRCUIT DESCRIPTION (MP3) G PCM output Interface The decoded audio data are output in serial PCM format. The interface consists of the following signals. ADOPCM Serial data Output SCKTPCM Serial Clock output LRCLKLeft/right Channel selection Clock The outpu

23、t samples preciision is selectable from 16 to 24 bits/word, by setting the output precision with PCMCONF (16, 18, 20 and 24 bits mode) register. Data can be output either with the most significant bit first (MS) or least signifi- cant bit first (LS), selected by writing into a flag of the PCM-CONF r

24、egister. Figure 5 gives a description of the several STA013 PCM Output Formats. The sample rates set decoded by STA013 is described Table 1. MPEG 1MPEG 2PMEG 2.5 482412 44.122.0511.025 32168 G STA013 Operation Mode The STA013 can work in two different modes, called Multimedia Mode and Broadast Mode.

25、 In Multimedia Mode, STA013 decodes the incoming bit- stream, acting as a master of the data communication from the source to itself. This control is done by a specific buffer management, con- trolled by STA013 embedded software. The data source, by monitorng the DATA_REQ line, send to STA013 the in

26、put data, when the signal is high (default configuration). The communication is stopped when the DATA_REQ line is low. In this mode the fractional part of the PLL is disabled and the audio clocks are generated at nominal rates. Fig. 9 describes the default DATA_REQ sigal behaviour. Programming STA01

27、3 it is possible to invert the polarity of the DATA_REQ line (register REQ_POL). In Broadcast Mode, STA013 works receiving a bitstream with the input speed regulated by the source. In this config- uration the source has to guarantee that the bitrate is equivalent to the nominal bitrate of the decode

28、d stream. To compensate the difference between the nominal and the real sampling rates, the STA013 embedded software controls the fractional PLL operation. Portable or Mobile applications need normally to operate in Broadcast Mode. In both modes the MPEG Synchronisation is automatic and transparent

29、to the user. To operate in Multimedia mode, the STA013, pin nr. 8, SCR-INT must be connected to VDD on the application board. G STA013 Decoding States There are three different decoder states: Idle, Init, and Decode. Commands to change the decoding states are described in the STA013 I2C registers de

30、scription. Idle Mode In this mode the decoder is waiting for the RUN command. This mode should be used to initialise the configuration regis- ter of the device. The DAC connected to STA013 can be ini- tialised during this mode (set MUTE to 1). PLAYMUTEClock StatePCM Output X0Not Runnig0 X1Runnig0 Ta

31、ble 1 MPEG Sampling rates (kHz) Fig. 5 PCM output Formats Fig. 6 LRCKT SDO SDO LRCKT SDO SDO SDO SDO 16 SCLK Cycles 16 SCLK Cycles 16 SCLK Cycles 16 SCLK Cycles 16 SCLK Cycles M S M S L S L S M S L S M S L S M S L S M S L S M S L S M S L S PCM_ORD=0 PCM_PREC=16bit mode PCM_ORD=1 PCM_PREC=16bit mode

32、32 SCLK Cycles 32 SCLK Cycles 32 SCLK Cycles 32 SCLK Cycles 32 SCLK Cycles M S L S 0 M S L S 0 M S L S 0 M S L S 0 PCM_FORMAT=1 PCM_DIFF=1 M S L S 0 M S L S 0 M S L S 0 M S L S 0 PCM_FORMAT=0 PCM_DIFF=0 M S L S MSB M S L S MSB M S L S MSB M S L S MSB PCM_FORMAT=1 PCM_DIFF=0 M S L S 00 M S L S 00 M S

33、 L S 00 M S L S 00 PCM_FORMAT=0 PCM_DIFF=1 DATA_REQ SOURCE SEND DATA TO STA013 SOURCE STOPS TRANSMITTING DATA SOURCE STOPS TRANSMITTING DATA KDC-MP6090R/MP7018/MP8017 14 CIRCUIT DESCRIPTION (MP3) Init Mode “PLAY” and “MUTE” changes are ignored in this mode. The internal state of the decoder will be

34、updated only when the decoder changes from the state “init” to the state “decode”. The “init” phase ends when the first decoded samples are at the output stage of the device. Decode Mode This mode is completely described by the following table. PLAY MUTECiook StatePCM OutputDecoding 00Not Running0No

35、 01Running0No 10RunnigDecoded SamplesYes 11Running0Yes I I2C BUS SPECIFCATION The STA013 supports the I2C protocol. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiv- er. The device that controls the data transfer is known

36、as the master and the others as the slave. The master always starts the transfer and provides the serial clock for syn- chronisation. The STA013 is always a slave device in all its communications. G COMMUNICATION PROTOCOL Data transition or change Data changes on the SDA line must only occur when th

37、e SCL clock is low. SDA transition while the clock is high are used to identify START or STOP condition. Start condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for d

38、ata transfer. Stop condition STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communications between STA013 and the bus master. Acknowledge bit An acknowledge bit is used to indicate a sucoessf

39、ul data transfer. The bus transmitter, either master or slave, releases the SDA bus after sending 8 bit of data. During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of 8 bits of data. Data input During the data input the STA013 samples the SDA signal on the risin

40、g edge of the ciock SCL. For correct device operation the SDA signal has to be sta- ble during the risng edge of the clock and the data can change only when the SCL line is low. G DEVICE ADDRESSING To start communication between the master and the STA013, the master must initiate with a start condit

41、ion. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifi- er, corresponding to the I2C bus definition. For the STA013 these are fixed as 1000011. The 8th b

42、it (LSB) is the read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. After a START condition the STA013 identifies on the bus the device address and, if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The following byte after th

43、e device identification byte is the internal space address. G WRITE OPERATION (see Fig. 7) Following a START condition the master sends a device select code with the RW bit set to 0. The STA013 acknowledges this and waits for the byte of internal address. After receiving the internal bytes address t

44、he STA013 again responds with an acknowledge. Byte write In the byte write mode the master sends one data byte, this is acknowledged by STA013. The master then termi- nates the transfer by generating a STOP condition. Multibyte write The multibyte write mode can start from any internal address. The

45、transfer is terminated by the master gener- atinga STOP condition. DEV-ADDRSUB-ADDRDATA IN RWSTOP ACKACKACK START BYTE WRITE DEV-ADDRSUB-ADDRDATA IN RWSTOP ACKACKACK DATA IN ACK START MULTIBYTE WRITE Fig. 7 Write Mode Sequence KDC-MP6090R/MP7018/MP8017 15 CIRCUIT DESCRIPTION (MP3) G READ OPERATION (

46、see Fig. 8) Curent byte address read The RTA013 has an internal byte adress counter. Each time a byte is written or read, this counter is incremented. For the current byte address read mode, following a START condition the master sends the device address with the RW bit set to 1. The STA013 acknowle

47、dges this and outputs the byte address by the internal byte address counter. The master does not acknowledge the received byte, but terminates the transfer with a STOP condtion. Sequential address read This mode can be intiated with either a curret address read or a rendom address read. However in t

48、his case the mas- ter does acknowledge the data byte output and the STA013 countinuse to output the next byte in sequence. To terminate the streams of byte the master does not anknowledge the last receivesd byte, but terminates the transfer with a STOP condition. The output data stream is from conse

49、ctive byte address, with the interminal byte address counter automatically incremented after one byte output. DEV-ADDR DEV-ADDRSUB-ADDR DATA RWSTART STARTSTART STOP ACK RWRWSTOP STOPRW=HIGH ACK ACKACKACK ACKACKNO ACK NO ACK DEV-ADDRDATA DATA NO ACK DEV-ADDR START DEV-ADDRDEV-ADDRSUB-ADDR STARTSTARTRW ACK RWSTOP ACKACKACKNO ACKACK DATADATADATA DATADATA CURRENT ADDRESS READ RANDOM ADDRESS READ SEQUENTIAL CURRENT READ SEQUENTIAL RANDOM READ Fig. 8 Read Mode Sequence I MP3 Playing Procedure 1. A request for read (minute, second, frame) occurs in the MP3 decoder control