Kenwood-RXDV555-cs-sm 电路图 维修手册.pdf
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1、70% MINI HiFi COMPONENT SYSTEM RXD-V555/V555-H/V757 SERVICE MANUAL 2001-10 PRINTED IN KOREA B51-5764-00 (K/K) 404 * Refer to parts list on page 28. In compliance with Federal Regulations, following are repro- duction of labels on, or inside the product relating to laser product safety. KENWOOD-Corp.
2、 certifies this equipment conforms to DHHS Regulations No.21 CFR 1040. 10, Chapter 1, subchapter J. DANGER : Laser radiation when open and interlock defeated. AVOID DIRECT EXPOSURE TO BEAM. Dress ring (A21-3957-08) FRT cab assy * (A60-) Front glass * (B10-) Panel(VCD) (A60-2220-08) Knob(VOLUME) (K27
3、-2470-08) Cassette lid(R) (A21-3959-08) Phone jack (E11-0942-08) Cassette lid(L) (A21-3958-08) Jack(MIC) (E11-0953-08) *Refer to page 2 if you want to know system configuration. (XD-V555/XD-757)* Knob(MIC VOLUME) (K29-8153-08) RadioFans.CN 收音机爱 好者资料库 AC Plug Adaptor (1) (E03-0115-05) Use to adapt th
4、e plug on the power cord to the shape of the wall outlet. (Accessory only for regions where use is necessary.) AM Loop Antenna(1) (T90-0879-08) AA size battery(2) (UM/SUM-3, R6, HP-7 or similar) Remote Control(1) (A70-1574-08) FM Antenna(1) (T90-0883-08) Video Cable(1) (E30-7255-08) RXD-V555/V757 2
5、CONTENTS / ACCESSORIES CONTENTS / ACCESSORIES . 2 EXTERNAL VIEW.3 ADJUSTMENT.7 PC BOARD . 8 SCHEMATIC DIAGRAM . 16 EXPLODED VIEW .26 PARTS LIST.28 SPECIFICATIONS .Back cover Contents Accessories SYSTEMMAIN UNITDESTINATIONSPEAKER XD-V858RXD-V757MILS-N90VS XD-V757RXD-V757MILS-N70VS XD-V555RXD-V555MILS
6、-N50VS XD-V555-HRXD-V555-HMLS-N50VS-H System Configurations The marking of products using lasers (Except for some areas) The marking is located on the rear panel and says this product has been classified as Class 1. It means that there is no danger of hazard- ous radiation outside the product CLASS
7、1 LASER PRODUCT Cautions RadioFans.CN 收音机爱 好者资料库 RXD-V555/V757 3 EXTERNAL VIEW ANTENNA AM LOOP FM 75 VIDEO /AUX VIDEO OUT SPAN SELECTOR 230V 240V FM 50kHz AM 9kHz FM 100kHz AM 10kHz + +- - L SPEAKERS RATED SPEAKER IMPEDANCE: 6 OHMS MIN. R LR Cabinet(TOP) (A02-3014-08) AC power cord (E30-7227-08) RCA
8、 socket (E02-0021-08) Lock terminal board (E70-0144-08) FM Antenna (E70-0145-08) Switch (S62-0086-08) Pin jack (E63-1219-08) AC power cord bushing (J42-0338-08) Pin assy (E40-8933-08) RadioFans.CN 收音机爱 好者资料库 RXD-V252/V252-H 4 CIRCUIT DESCRIPTION Block Diagram for MPEG1 Video/Audio Processing RAS# Pr
9、ocessorLA(17:0) DRAM InterfaceDA(8:0) InterfaceLD(7:0) Huffman DBUS(15:1) LCS3#, LCS#(1:0) RISC Decoder DOU#DRAM LWR# Processor 2Kx32 ROMDWE# LOE# 2x32 SRAMCAS# ACLKAUX(7:1)AUX SerialATCLK MPEG AudioAIN Serial Audio Processor InterfaceAOUT Interface ARFS64x32 ROMYUV(7:0) ATFS32x32 SRAMPCLK2XScreen A
10、RCLKRegistersVideo OutputPCLK VSYNC HSYNC TDMSEL-PLL(1:0) TDM InterfaceTDMCLK Interface On Screen TDMDR DisplayCPUCLKMisc TDMFS DRAM DMA RESET# Controller Port No.Port NameI/OFunction 1,31,51VCC3-Supply voltage for 3.3V. 2RAS#ODRAM row address strobe (active low). 3DWE#ODRAM write enable (active low
11、). 412MA(08)ODRAM multiplexed row and column address bus. 1328DBUS(015)I/ODRAM data bus. 29RESET#ISystem reset (active low). 30,50,80,100GND-Ground. 3239YUV(07)O Y is luminance, UV are chrominance data bus for screen video interface. YUV(07) for 8 bit YUV mode. 40VSYNCI/O Vertical sync for screen vi
12、deo interface, programmable for rising or falling edge. 41HSYNCI/O Horizontal sync for screen video interface, programmable for rising or falling edge. 42CPUCLKIRISC and system clock input. 43PCLK2XI/OPixel clock: two times the actual pixel clock for screen video interface. 44PCLK I/OPixel clock qua
13、lifier in for screen video interface. 4549,52,53,54AUX(07)I/OAuxiliary control pins (AUX0 and AUX1are open collectors). 5562LD(07)I/ORISC interface data bus. 63LWR#OUnused. 64LOE#ORISC interface output enable (active low). 65,66,67LCS(3,1,0)#ORISC interface chip select (active low). 6879,8287LA(017)
14、ORISC interface address bus. 81VCC-Digital supply voltage for 5.0V. 88ACLKI/O Master clock for external audio DAC(8.192MHz, 11.2896MHz, 12.288MHz, 16.9344MHz, and 18.432MHz). ODual-purpose pin. AOUT is the audio interface serial data output. Pins SEL -PLL(1: 0) select phase-lock loop(PLL) clock freq
15、uency 89AOUT/SEL/PLL0ICPUCLK for the Visba : 00 = bypass PLL 01 = 54MHz PLL 10 = 67.5MHz PLL 11 = 81MHz PLL 90ATCLKI/OAudio transmit bit clock. ODual-purpose pin. ATFS is the audio interface transmit frame sync. 91ATFS/SEL/PLL1I Pins SEL -PLL(1: 0) select phase-lock loop(PLL) clock frequency CPUCLK
16、for the Visba. See the SEL -PLL0 pin above for the settings. 92DOEO Dual-purpose pin. DRAM output enable (active low)/DRAM multiplexed row and column address bus. 93AINIAudio interface serial data input. 94ARCLKIAudio receive bit clock. 95ARFSIAudio interface receive frame sync. 96TDMCLKITDM interfa
17、ce serial clock. 97TDMDRITDM interface serial data receive. 98TDMFSITDM interface frame sync. 99CAS#ODRAM column address strobe bank 0 (active low). Port Function of MPEG1 Video/Audio Processing : ES3880 (ICM2) RXD-V252/V252-H 5 CIRCUIT DESCRIPTION Port No.Port NameI/OFunction 1,25,26,31,72 75,77,91
18、,100 VSSIGround. 5,16,32,66 73, 78,90 VCCISupply voltage for 5.0v. 6DSC CIClock for programming to access internal registers. 7AUX0I/OUnused. 9AUX1I/OServo reverse or control pin. 11AUX2I/OServo LD ON or control pin. 70AUX3I/OUnused. 69AUX4I/OServo CCW/Close or control pin. 68AUX5I/OUnused. 67AUX6I/
19、OServo XLAT or control pin/VFD DO. 14AUX7I/OServo BRKM/Sense or control pin/VFD DI. 18AUX8I/OServo Mute/Open or control pin/VFD CLK. 20AUX9I/OServo SQS0 or control pin. 34AUX10I/OUnused. 35AUX11I/OUnused. 36AUX12I/OUnused. 38AUX13I/OSerial interrupt/CD Mute or control pin. 39AUX14I/OUnused. 40AUX15I
20、/OUnused. 8,81,83,85 93,95,97,99 DSC D(70)I/OData for programming to access internal registers. 10DSC SIStrobe for programming to access internal registers. 12DCLKODual purpose pin. DCLK is the MPEG decoder clock. EXT CLKIEXT CLK is the external clock EXT CLK is an input during bypass PLL mode. 13RE
21、SET BIVideo reset (active low). 15MUTEOAudio mute. 17MCLKIAudio master clock. 19TWSIDual purpose pin. TWS is the transmit audio frame sync. SPLL OUTOSPLL OUT is the select PLL output. 21TSDITransmit audio data input. 22TBCKITransmit audio bit clock. ODual purpose pin. RWS is the receive audio frame
22、sync. Pins SEL PLL (1,0) select the PLL clock frequency for the DCLK output. 23RWS SEL PLL1 SEL PLL0 DCLK SEL PLL1 I0 0 Bypass PLL (input mode) 0 1 27MHz (output mode) 1 0 32.4MHz (output mode) 1 1 40.5MHz (output mode) 24RSTOUT BOReset output (active low). 24,2730 76 NC-Unused. RSDODual purpose pin
23、. RSD is the receive audio data input. 33 SEL PLL0ISEL PLL0 along with SEL PLL1 select the PLL clock frequency for the DCLK output. 37RBCKODual purpose pin. RBCK is the receive audio bit clock. SER INISER IN is the serial input DSC mode. 41,51AGNDIAudio analog ground. 42VCMIADC common mode reference
24、 (CMR) buffer output. 43VREFPIDAC and ADC maximum reference. 44VCCAAIAnalog VCC(5V). 45,46AOR+, AOR-ORight channel output. 47,48AOL-, AOL+OLeft channel output. 49MIC1IMicrophone input 1. 50MIC2IMicrophone input 2. Port Function of DAC The value shown in ( ) is the voltage measured at the moment of S
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