Philips-DVDR-5590-H-Service-Manual(1) 电路图 维修手册.pdf

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1、Published by KC-TE 0808 V Wrong user input 40202 Address is not dividable by 4 Example DS: 402 0 xa1000010 0 xad112222 040200: Test OK EN 273139 785 335315.Firmware Upgrading Wrong user input 40302 Address is not dividable by 4 Example DS: 403 0 xa1000010 040300: Value read = 0 xAD112222 Test OK Nuc

2、leus Name DS_SDRAM_DmaWriteRead Nucleus Number 404 Description Write a pattern to the entire RAM using DMA and check the data Technical - Check if the Stack pointer is not in the write range - Clear a 64kb block and then fill it with a pattern - Initialise the DMA controller and write the data to th

3、e SDRAM - Then check if all the data was written correctly (except descriptor tables) - Repeat the process 4 times with 4 different patterns Execution Time 24 seconds User Input None. Error Number Description 40400 Writing to the RAM succeeded 40401 Stack area definition ERROR! 40402 DMA controller

4、could not be initialised. 40403 Not all data was transferred correctly Example DS: 404 040400: Test OK EN 283139 785 33531Firmware Upgrading Wrong user input 50202 Address is not dividable by 4 Example DS: 502 0 xb8000000 050200: Value read = 0 x3C08A000 Test OK Nucleus Name DS_FLASH_ChecksumProgram

5、 Nucleus Number 503 Description Check the checksum of the application partitions by recalculating and comparing partition checksums Technical - Determine the number of segments - Find the application in each segment and determine its checksum - Check whether the checksums stored match the newly calc

6、ulated Execution Time 6 seconds User Input None Error Number Description 50300 The checksum is valid, the test succeeded 50301 The checksum is invalid Example DS: 503 050300: BootCode checksum is: 0 xBABE5B6F, which is correct Diagnostics checksum is: 0 xBABEBAFF, which is correct Download checksum

7、is: 0 xBABEEDBF, which is correct Application checksum is: 0 xBABE8EEC, which is correct Test OK EN 293139 785 335315.Firmware Upgrading however, the SYSCLK output remains active. If the LPS input remains low for more than 26 s (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power disa

8、bled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state upon hardware reset. The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1, and is considered inactive if either the LPS input is in

9、active or the LCtrl register bit is cleared to 0. LREQ148CMOSILLC request input. The LLC uses this input to initiate a service request to the TSB41AB1. Bus holder is built into this terminal. PC0 PC1 PC2 20 21 22 16 17 18 CMOSIPower class programming inputs. On hardware reset, these inputs set the d

10、efault value of the power class indicated during self-ID. Programming is done by tying these terminals high or low. Refer to Table 9 for encoding. PD1412CMOSIPower-down input. A high on this terminal turns off all internal circuitry except the cable-active monitor circuits, which control the CNA out

11、put (64-terminal PAP package only). Asserting the PD input high also activates an internal pulldown on the RESET terminal to force a reset of the internal control logic. (PD is provided for legacy compatibility and is not recommended for power management in place of IEEE 1394a-2000 suspend/resume LP

12、S and C/LKON features.) EN 1443139 785 335318.IC Internal Block Diagrams TERMINAL TYPEI/ODESCRIPTION NAMEPAP NO.PHP NO. TYPEI/ODESCRIPTION PLLGND57, 5841SupplyPLL circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane. PLLVDD5640SupplyPLL ci

13、rcuit power terminals. A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10 F filtering capacitors are also recommended. This supply terminal is separated from DVDD and AVDD inside the device to provide noise

14、isolation. It should be tied at a low-impedance point on the circuit board. R0 R1 40 41 33 34 BiasCurrent setting resistor terminals. These terminals are connected through an external resistor to set the internal operating currents and cable driver output currents. A resistance of 6.34 k 1.0% is req

15、uired to meet the IEEE Std 1394-1995 output voltage limits. RESET5337CMOSILogic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to VDD is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in the

16、Application Information section). The RESET terminal also incorporates an internal pulldown which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and may also be driven by an open-drain type driver. SE2823CMOSITest control input. This input is used in

17、 manufacturing test of the TSB41AB1. For normal use this terminal may be tied to GND through a 1-k pulldown resistor or it may be tied to GND directly. SM2924CMOSITest control input. This input is used in manufacturing test of the TSB41AB1. For normal use this terminal should be tied to GND. SYSCLK2

18、1CMOSOSystem clock output. Provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC. TESTM2722CMOSITest control input. This input is used in manufacturing test of the TSB41AB1. For normal use this terminal should be tied to VDD. TPA+3730CableI/OTwisted-pair cable A differenti

19、al signal terminals. Board traces from the pair of positive and negative differential signal terminals should be kept matched and as TPA3629CableI/O positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable con

20、nector. TPB+3528CableI/OTwisted-pair cable B differential signal terminals. Board traces from the pair of positive and negative differential signal terminals should be kept matched and as TPB3427CableI/O positive and negative differential signal terminals should be kept matched and as short as possi

21、ble to the external load resistors and to the cable connector. TPBIAS3831CableI/OTwisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable co

22、nnection. XI XO 59 60 42 43 CrystalCrystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used (see crystal selection in the Application Inf

23、ormation section). When an external clock source is used, XI should be the input and XO should be left open, and the clock must be supplied before the device is powered on. EN 1453139 785 335318.IC Internal Block Diagrams IC7301 TPS2051AD - CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES BLOCK DIAGRAM T

24、PS2041A OUT OC IN EN GND Current Limit Driver UVLO Charge Pump CS Thermal Sense Power Switch Active high for TPS205xA series Current sense TPS2042A Thermal Sense Driver Current Limit Charge Pump UVLO CS Driver Current Limit CS Thermal Sense Charge Pump Power Switch GND EN1 IN EN2 OC1 OUT1 OUT2 OC2 A

25、ctive high for TPS205xA series Current sense Figure 8-6 PIN CONFIGURATION 1 2 3 4 8 7 6 5 GND IN IN EN OUT OUT OUT OC TPS2041A, TPS2051A D PACKAGE (TOP VIEW) 1 2 3 4 8 7 6 5 GND IN EN1 EN2 OC1 OUT1 OUT2 OC2 TPS2042A, TPS2052A D PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GNDA IN1 EN1 E

26、N2 GNDB IN2 EN3 EN4 OC1 OUT1 OUT2 OC2 OC3 OUT3 OUT4 OC4 TPS2044A, TPS2054A D PACKAGE (TOP VIEW) All enable inputs are active high for the TPS205xA series. NC No connect 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GNDA IN1 EN1 EN2 GNDB IN2 EN3 NC OC1 OUT1 OUT2 OC2 OC3 OUT3 NC NC TPS2043A, TPS2053A D PACKA

27、GE (TOP VIEW) Figure 8-7 EN 1463139 785 335318.IC Internal Block Diagrams PIN DESCRIPTION TPS2041A and TPS2051A TERMINAL NAME NO.I/ODESCRIPTION NAME TPS2041ATPS2051A EN4IEnable input. Logic low turns on power switch. EN4IEnable input. Logic high turns on power switch. GND11IGround IN2, 32, 3IInput v

28、oltage OC55OOvercurrent. Logic output active low OUT6, 7, 86, 7, 8OPower-switch output TPS2042A and TPS2052A TERMINAL NAME NO.I/ODESCRIPTION NAME TPS2042ATPS2052A EN13IEnable input. Logic low turns on power switch, IN-OUT1. EN24IEnable input. Logic low turns on power switch, IN-OUT2. EN13IEnable inp

29、ut. Logic high turns on power switch, IN-OUT1. EN24IEnable input. Logic high turns on power switch, IN-OUT2. GND11IGround IN22IInput voltage OC188OOvercurrent. Logic output active low, for power switch, IN-OUT1 OC255OOvercurrent. Logic output active low, for power switch, IN-OUT2 OUT177OPower-switch

30、 output OUT266OPower-switch output EN 1473139 785 335318.IC Internal Block Diagrams IC7500 SAA7136AE MULTISTANDARD AUDIO/VIDEO DECODER BLOCK DIAGRAM Fig.2 System Block Diagram of SAA7136 SAICO S-video Analog Sound Input Sound Decoder Analog 16-bit Stereo ADC Front End NF/Audio Stereo BUFFER Analog V

31、ideo ADCFront End Video 10-Bit AI31 AI32 AI33 SSIF CVBS Sound Audio Inputs Port B TS data Digital Inputs Data IR in Digital Video Decoder Comb Filter Video Scaler Format DACs Stereo I2S Audio Output MUX I2S Audio Stereo VIP Host DSP I2S SPDIF Dual FM/NICAM BTSC EIAJ dBx expander(*) Volume control Ba

32、ss, Treble and Balance SRC Incredible Sound I2S I2S SPDIF SPDIF VIP Analog Video ADCFront End Video 10-Bit AI40P AI41 AI42 AI43 Analog Video ADCFront End Video 10-Bit AI11 AI12 AI13 IF_POS(*) Analog Video ADCFront End Video 10-Bit AI21 AI22 AI23 NAICO Analog Control Input Video Unit Control Unit Com

33、ponent Processing SDTV/HD Sync. VBI Slicer Digital Low IF IF(*) H- Scaler PRE V- Scaler Task A (Video) Task B RAW VBI Scaler Event Handler EDDI D C I O S T P S C A L E R Dig. Video Output Dig. Video IN DI_A_x Scaler PLL Port D Port C Video DAC ITU VMI VIP Video I2C Slave TS/PS In Remote Control VIP

34、Host Port with I2C Bus IR out Remote ControlReceiver Transmitter PHI PHI Bus VIP_Host_Audio VIP_Host_Audio Initiator INT_A IRQ & Main Control audio conversion TS - Out & Audi - In Silent I2C Bus Sound Audio Outputs low IF SSIF & RGB(*)/YPbPr Video Inputs Digital Programming and Control Ports M ADC X

35、 U 3-Bit FSW AV D-C FSW AV/DC Status bits Audio ProcessingVideo Processing Programming and Control Processing Programming AUXInputs Port A Video Output Ports DI_E_x AI40N IF_NEG(*) I2S Audio DAC CVBS Register Array I2C read back PHI FIFO Processing H,V Soft Mixer 8-bit/ 10-bit IN1_Left IN1_Right IN3

36、_Left IN3_Right IN2_Left IN2_Right OUT2_Left OUT2_Right OUT1_Left OUT1_Right DVO_D_X DVO_C_X SSIF (*) CVBS (*) S_IOUTP S_IOUTN V_IOUTP V_IOUTN DI_B_x (DI_A_x) (DI_B_x) (*)only SAA7136E, (*) only SAA7136E/AE/DE, only SAA7136E/AE/BE (*) Figure 8-8 EN 1483139 785 335318.IC Internal Block Diagrams PIN C

37、ONFIGURATION Table 1 Pin Confi guration (BGA 256 top view) 12345678910111213141516 AAUX3A NCAUX2BAUX1AIN2_LeftVDDA(3V3)OUT1_LeftIF_AGCI2S_I_1_WSI2S_O_SRST_ OUT_N VSSD(3V3)VIP_HCT L VSSDVIP_D6VIP_D5 BAUX3B NCAUX2AIN3_LeftIN2_RightVRPOS_ADCOUT1_RightNCVSSDSPDIF_IIR_OUTVDDD(3V3)VIP_CLKVDDD(3V3)VIP_D3VI

38、P_D4 CAGND1 VSYNCAUX1BVREF_ADCIN1_LeftVRNEG_ADCVDDA(3V3)I2S_I_2_SDVDDD(3V3)SPDIF_OVDDD(1V8)GPIO_0VIP_D7VDDD(3V3)VSSDVIP_D2 DVDDA (3V3) VDDA(1V8)VSSAIN3_RightIN1_RightVREF_DACVDDD(1V8)I2S_I_2_SCKI2S_O_ SD_AUX VDDD(1V8)IR_INVIP_RSNDI_E_7PP_SELVIP_D0VIP_D1 EV_IOUTN V_IOUTPS_IOUTNS_IOUTPVSSAVSSAOUT2_Rig

39、htI2S_I_2_WSI2S_O_ AMCLK NCGPIO_1VSSDVDDD(1V8)VDDD(3V3)VSSDDI_E_6 FAI11 IF_NEGIF_POSDAC_ Bias VDDA(3V3)VREF0OUT2_LeftI2S_I_1_SDI2S_O_SCKVSSDVSSDDI_E_1DI_E_2DI_E_3DI_E_4DI_E_5 GAI13 AI12VDDA(3V3)VSSAVSSAVDDA(3V3)VSSDI2S_I_1_SCKI2S_O_WSVSSDDI_B_VSDI_B_DQDI_A_8DI_A_9DI_E_0VDDD(3V3) HAI23 AI22AI21VSSAVD

40、DA(3V3)AI1DNCVSSDDI_B_HSNCNCNCNCNCNCVDDD(3V3) JNC VDDA(1V8)VSSAVDDA(3V3)AI2DVSSAVDDA(3V3)NCVSSDDI_A_CLKVDDD(1V8)VSSDDI_B_5DI_B_6DI_B_7DI_B_ CLK KVSSA VSSAAOUT2VDDA(3V3)AOUT1RES_REF_VNCDI_A_2DI_A_3VSSDDI_B_0DI_B_1DI_B_2DI_B_3DI_B_4VDDD(3V3) LAI33 AI32AI31VDDA(3V3)VSSAAGND2XTOUTSI_VSYNCDI_A_4DI_A_ LOC

41、K VSSDDVO_ODE V DVO_DQDVO_D_C LK VDDD(3V3)VSSD MVSSA VSSAVDDA(3V3)AI3DNCNCD_CON_1NCVSSDDI_A_VALDVO_C_0VSSDVDDD(3V3)VSSDDVO_VSGPIO_2 NAI41 AI40NAI40PVDDA(3V3)SDAINT_AD_CON_2VSSDDI_A_5VDDD(1V8)VDDD(1V8)VSSDDVO_C_6DVO_D_7DVO_CLK _C DVO_HS PNC AI43AI42TDOSCL_SILENTCEVDDD(1V8)DI_A_0DI_A_6VDDD(3V3)DVO_C_1

42、DVO_C_3DVO_C_7DVO_D_0DVO_D_5DVO_D_6 RVDDA(3V3) AI4DTCKTDISDA_SILENTVSSAVDDA(1V8)DI_A_1VDDD(3V3)VSSDDVO_C_2DVO_C_4VDDD(3V3)DVO_D_1DVO_D_3VSSD TVSSA TRST_NTMSSCLNCXTALIXTALOVDDD(3V3)DI_A_7DI_A_SOPVDDD(3V3)DVO_C_5VSSDDVO_D_2DVO_D_4VDDD(3V3) Analog Processing PinsDigital Processing Pins Figure 8-9 EN 14

43、93139 785 335318.IC Internal Block Diagrams 8.3. HDMI Board 8.3.1 IC7100 - FLI2310 - Faroudja Digital Video Format Converter (HDMI PCBA 3139 248 89141) BLOCK DIAGRAM Figure 9-25: FLI2310 Simplified Internal Block Diagram Input Processor with Auto Sync and auto Adjust Noise Reducer, Deinterlacer, Fra

44、me Rate Converter and SDRAM interface Port 2 8-bit 656 Input Port 1 8/16/24-bit RGB/YCrCb Input Clock Generation PLLs 2Mx32 SDRAM (external) Vertical and Horizontal Scalers Vertical and Horizontal Enhancers Output Processor 16/20/24-bit RBG/YCrCb Digital Outputs EN 1503139 785 335318.IC Internal Blo

45、ck Diagrams Figure 8-14 PIN CONFIGURATION Figure 3.1: Pinout Information 1 5 5 1 5 0 1 4 5 1 4 0 1 3 5 1 3 0 1 2 5 1 2 0 1 1 5 1 1 0 1 0 5 1 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 5 6 0 1 0 0 9 5 9 0 8 5 8 0 7 5 7 0 2 0 5 1 9 5 2 0 0 1 6 0 1 6 5 1 7 0 1 7 5 1 8 0 1 8 5 1 9 0 HSYNC1_PORT1 VDD1 B

46、/Cb/D1_0 VSS IN_CLK1_PORT1 FIELD ID1_PORT1 VSYNC1_PORT1 HSYNC2_PORT1 IN_CLK2_PORT1 FIELD ID2_PORT1 VSYNC2_PORT1 B/Cb/D1_6 B/Cb/D1_5 B/Cb/D1_4 B/Cb/D1_3 B/Cb/D1_2 B/Cb/D1_1 B/Cb/D1_7 VDDcore1 VSScore R/Cr/Cb Cr_0 R/Cr/Cb Cr_6 R/Cr/Cb Cr_5 R/Cr/Cb Cr_4 R/Cr/Cb Cr_3 R/Cr/Cb Cr_2 R/Cr/Cb Cr_1 R/Cr/Cb Cr

47、_7 VDD2 VSS G/Y/Y_0 G/Y/Y_1 G/Y/Y_6 G/Y/Y_5 G/Y/Y_4 G/Y/Y_3 G/Y/Y_2 G/Y/Y_7 VDDcore2 VSScore IN_SEL TEST DEV_ADDR1 DEV_ADDR0 SCLK SDATA RESET_N VDD3 VSS SDRAM DATA(0) SDRAM DATA(2) SDRAM DATA(1) SDRAM DATA(3) SDRAM DATA(10) SDRAM DATA(9) SDRAM DATA(8) SDRAM DATA(7) SDRAM DATA(6) SDRAM DATA(5) SDRAM

48、DATA(4) SDRAM DATA(17) SDRAM DATA(16) SDRAM DATA(15) SDRAM DATA(14) SDRAM DATA(12) SDRAM DATA(13) SDRAM DATA(11) VDD4 VSS VDDcore3 VSScore SDRAM DATA(20) SDRAM DATA(19) SDRAM DATA(18) SDRAM DATA(31) SDRAM DATA(30) SDRAM DATA(29) SDRAM DATA(28) SDRAM DATA(26) SDRAM DATA(27) SDRAM DATA(25) SDRAM DATA(

49、24) SDRAM DATA(23) SDRAM DATA(21) SDRAM DATA(22) VDDcore4 VSScore VSS VDD5 TEST IN SDRAM ADDR(10) SDRAM ADDR(5) SDRAM ADDR(4) SDRAM ADDR(3) SDRAM ADDR(6) SDRAM ADDR(7) SDRAM ADDR(8) SDRAM ADDR(9) VDDcore5 VSScore SDRAM ADDR(0) SDRAM ADDR(1) SDRAM ADDR(2) SDRAM WEN B/U/Pb_OUT_7 VDDcore7 VSScore R/V/Pr_OUT_7 VDD8 VSS G/Y/Y_OUT_7 G/Y/Y_OUT_1 G/Y/Y_OUT_2 G/Y/Y_OUT_3 G/Y/Y_OUT_4 G/Y/Y_OUT_5 G/Y/Y_OUT_6 G/Y/Y_OUT_0 R/V/Pr_OUT_0 R/V/Pr_OUT_1 R/V/Pr_OUT_2 R/V/Pr_OUT_3 R/V/Pr_OUT_4 R/V/Pr_OUT_5 R/V/Pr_OUT_6 B/U/Pb_OUT_0 B/U/Pb_OU