Philips-DVDR-7300-H-Service-Manual(1) 电路图 维修手册.pdf

《Philips-DVDR-7300-H-Service-Manual(1) 电路图 维修手册.pdf》由会员分享，可在线阅读，更多相关《Philips-DVDR-7300-H-Service-Manual(1) 电路图 维修手册.pdf（194页珍藏版）》请在收音机爱好者资料库上搜索。

1、Published by KC-TE 0636 AV Systems Printed in the Netherlands Subject to modifi cation EN 3139 785 31532 DVDR5350H/02/05/19HDD Wrong user input 40202 Address is not dividable by 4 Example DS: 402 0 xa1000010 0 xad112222 040200: Test OK Nucleus Name DS_SDRAM_Read Nucleus Number 403 Description Read f

2、rom a specific un-cached memory address Technical -Decode the user input and check the ranges -Read from the SDRAM and return this info to the user Execution Time Less than 1 second User Input The location from which the data must be read (SDRAM starts at address 0 xA0000000) Error Number Descriptio

3、n 40300 Reading from the SDRAM succeeded 40301 Reading from the SDRAM failed; Wrong user input 40302 Address is not dividable by 4 Example DS: 403 0 xa1000010 040300: Value read = 0 xAD112222 Test OK Nucleus Name DS_SDRAM_DmaWriteRead Nucleus Number 404 Description Write a pattern to the entire SDRA

4、M using DMA and check the data Technical -Check if the Stack pointer is not in the write range -Clear a 64kb block and then fill it with a pattern -Initialise the DMA controller and write the data to the SDRAM -Then check if all the data was written correctly (except descriptor tables) -Repeat the p

5、rocess 4 times with 4 different patterns Execution Time 24 seconds User Input None. Error Number Description 40400 Writing to the SDRAM succeeded 40401 Stack area definition ERROR! 40402 DMA controller could not be initialised. 40403 Not all data was transferred correctly Example DS: 404 040400: Tes

6、t OK EN 283139 785 31532Firmware Upgrading Wrong user input 50202 Address is not dividable by 4 Example DS: 502 0 xb8000000 050200: Value read = 0 x3C08A000 Test OK EN 293139 785 315325.Firmware Upgrading may be gated or used in a burst fashion. 27ISDATASerial Input, MSB first, containing two channe

7、ls of 16, 18, 20, and 24 bits of twos complement data per channel. 28IDVDDDigital Power Supply Connect to digital 5 V supply. Table I. Serial Data Input Mode IDPM1 (Pin 20)IDPM0 (Pin 21)Serial Data Input Format 00Right-Justified 01I2S-Compatible 10Left-Justified 11DSP EN 1743139 785 315329.Circuit-

8、and IC Description IC7007 - UDA 1361S - Analogue to Digital Converter BLOCK DIAGRAM, PIN DESCRIPTION AND CONFIGURATION handbook, full pagewidth UDA1361TS MGT451 1 VINL ADC DIGITAL INTERFACE DC-CANCELLATION FILTER DECIMATION FILTER CLOCK CONTROL 3 16 VINR ADC 13 DATAO 11 BCK 12 WS 6 SFOR 7 PWON 14 MS

9、SEL 15 10 VSSD 9 VDDD VSSA 5 VRP 4 VRN 2 Vref 8 SYSCLK VDDA Fig.1 Block diagram. PINNING SYMBOLPINDESCRIPTION VINL1left channel input Vref2reference voltage VINR3right channel input VRN4negative reference voltage VRP5positive reference voltage SFOR6data format selection input PWON7power control inpu

10、t SYSCLK8system clock 256, 384, 512 or 768fs VDDD9digital supply voltage VSSD10digital ground BCK11bit clock input/output WS12word select input/output DATAO13data output MSSEL14master/slave select VSSA15analog ground VDDA16analog supply voltage handbook, halfpage UDA1361TS MGT452 1 2 3 4 5 6 7 8 16

11、15 14 13 12 11 10 9 VINL Vref VINR VRN VRP SFOR PWON SYSCLK VDDD VSSD BCK WS DATAO MSSEL VSSA VDDA Fig.2 Pin configuration. Figure 9-8 EN 1753139 785 315329.Circuit- and IC description IC7200 - NJM2584M - 2-Input 1-Output 3 Circuit Video Switch BLOCK DIAGRAM IN1A IN2B IN3B 1 2 3 4 5 6 7 8 16 15 14 1

12、3 12 11 10 9 IN1B IN2A IN3A OUT1 OUT2 OUT3 NC CTL NC GND1 GND2 GND3 V+ BIAS CLAMP BIAS Figure 9-9 EN 1763139 785 315329.Circuit- and IC Description IC7201 - NJM2580M - 3-Channel Video Amplifi er BLOCK DIAGRAM 13 12 11 REF 1 2 3 4 7 5 6 14 8 10 9 V+ 1 GND1 GND2 GND3 VSAG VIN1 VIN2 VIN3 VOUT1 VOUT2 VO

13、UT3 Power Save BIAS 6dB AMP 75 Driver BIAS 75 Driver 6dB AMP CLAMP 75 Driver 6dB AMP V+ 2 V+ 3 Figure 9-10 EN 1773139 785 315329.Circuit- and IC description IC7203 - NJM2267M - Dual Video 6dB Amplifi er BLOCK DIAGRAM Figure 9-11 EN 1783139 785 315329.Circuit- and IC Description IC7408 - STV6618D - V

14、ideo Switch Matrix BLOCK DIAGRAM Sync Sep Bo. Clamp Y/CVBSIN_TUN Y/CVBSIN_TV Y/CVBSIN_AUX CVBSIN_ENC Bo. ClampG/YIN_AUX R/Pr/CIN_AUX B/PbIN_AUX Sync Sep Bo. ClampG/YIN_ENC R/Pr/CIN_ENC B/PbIN+ENC YIN_ENC CIN_TV CIN_ENC mute 0 dBY/CVBSOUT_REC Y/CVBSIN_TUN Y/CVBSIN_TV Y/CVBSIN_AUX CVBSIN_ENC YIN_ENC C

15、IN_TV CIN_ENC G/YIN_ENC G/YIN_AUX R/Pr/CIN_AUX B/PbIN_AUX R/Pr/CIN_ENC B/PbIN_ENC STV6618D Recorder mute 6 dB Y/CVBSOUT_TV Scart1 mute 6 dB Y/CVBSOUT_AUX Scart2 mute 6 dB R/Pr/COUT_TV mute 6 dB G/YOUT_TV Scart1 Scart1 mute 6 dB B/PbOUT_TV Scart1 Y/CVBS_TUN Y/CVBS_TV Y/CVBS_AUX CVBSIN_ENC YIN_ENC CIN

16、_TV CIN_ENC G/YIN_ENC G/YIN_AUX R/Pr/CIN_AUX B/PbIN_AUX R/Pr/CIN_ENC B/PbIN_ENC 0 dB FBOUT_TV SCL FBIN_AUX 0v 5v SDA C_GATE I2C bus Bo. Clamp Bo. Clamp Bo. Clamp Bo. Clamp Av. Clamp Av. Clamp Bot/sync/av. Bo/Sync Bot/sync Bot/sync/av. CVBSIN_TUN Y/CVBSIN_TV Y/CVBSIN_AUX CVBSIN_ENC YIN_ENC mute 6 dB

17、COUT_AUX Y/CVBSIN_AUX CVBSIN_ENC YIN_ENC CVBSIN_TUN Y/CVBSIN_TV CVBSIN_ENC YIN_ENC CIN_TV CIN_ENC CIN_ENC R/Pr/CIN_AUX R/Pr/CIN_ENC G/YIN_AUX G/YIN_ENC B/PbIN_AUX B/PbIN_ENC FBIN_AUX CIN_TUNAv. Clamp CIN_TUNCIN_TUN CIN_TUN DigOUT1 DigOUT2 DigOUT3 DigOUT4 DigOUT5 DigOUT6 Figure 9-12 EN 1793139 785 31

18、5329.Circuit- and IC description PIN DESCRIPTION AND CONFIGURATION gp Pin NumberSymbolDescription 1Y/CVBSIN_TUNY/CVBS Input from tuner 2digOUT3Digital output pin 3 3GND1ground, video inputs 4CVBSIN_ENCCVBS Input from Encoder 5DECVVideo decoupling capacitor 6CIN_ENCchroma Input from Encoder 7YIN_ENCY

19、 Input from Encoder 8Vcc+5 V Supply, video 9R/Pr/CIN_ENCRed or Pr or Chroma Input from Encoder 10G/YIN_ENCGreen or Y Input from Encoder 11B/PbIN_ENCBlue or Pb Input from Encoder 12GND2ground, video inputs 13B/PbIN_AUXBlue or Pb input from Auxiliary (scart2 or external cinch) 14DigOUT4Digital output

20、pin 4 15G/YIN_AUXGreen or Y input from Auxiliary (scart2 or external cinch) 16DigOUT5Digital output pin 5 17R/Pr/CIN_AUXRed or Pr or Chroma input from Auxiliary (scart2 or external cinch) 18DigOUT6Digital output pin 6 19Y/CVBSIN_AUXY/CVBS Input from Auxiliary (scart2 or external cinch) 20VCCB_RECVid

21、eo Output recorder Buffer Supply Pin 21Y/CVBSOUT_RECY/CVBS Output to Recorder 22GNDB_RECground , recorder buffer 23COUT_AUXChroma Output to Auxiliary (scart2 or external cinch) 24VCCB1Video Output Buffer Supply Pin 25Y/CVBSOUT_AUXY/CVBS Output to Auxiliary(scart2 or external cinch) 26GNDBGround vide

22、o buffer 27B/PbOUT_TVBlue or Pb output to TV (scart1 or external cinch) 28C_GATEexternal transistor command for bidirectinnal B/C scart I/O 29G/YOUT_TVGreen or Y output to TV (scart1 or external cinch) 30VCCB2Video Buffer 31R/Pr/COUT_TVRed or Pr or Chroma output to TV (scart1 or external cinch) 32VC

23、CB3Video Output Buffer Supply Pin 33Y/CVBSOUT_TVY/CVBS output to TV(scart1 or external cinch) 34FBOUT_TVFast Blanking Output to TV (scart1) 35FBIN_AUXFast blanking Input from auxiliary (scart2) 36VDD+5V digital supply 37SCLI2C Bus Clock 38SDAI2C Bus Data 39GNDDground digital 40CIN_TVChroma Input fro

24、m TV (scart1 or external cinch) 41Y/CVBSIN_TVY/CVBS Input from TV (scart1 or external cinch) 42digOUT1Digital output pin 1 43CIN_TUNChroma Input from Tuner 44digOUT2Digital output pin 2 EN 1803139 785 315329.Circuit- and IC Description IC7212 - NJM2234M - 3-Input Video Switch BLOCK DIAGRAM Figure 9-

25、13 IC7213 - NJM2235M - 3-Input Video Switch BLOCK DIAGRAM Figure 9-14 EN 1813139 785 315329.Circuit- and IC description 9.6.2 Digital Board IC7601 - NCP1571D - Low voltage Synchronous Buck Controller BLOCK DIAGRAM + UVLO COMP + + + Fault Latch Set Dominant + 0.25 V Error Amp + R S Q PWM Latch Reset

26、Dominant PWM COMP + OSC Art Ramp 80%, 200 kHz 0.525 V + 8.5 V/7.5 V + 0.980 V S R Q VCC GND VFB COMP GATE(H) GATE(L) PGDELAY PWRGD Non Overlap VCC + 0.88 V/0.69 V + + 0.25 V S R Q PGDELAY Latch Set Dominant + + 3.3 V 12 A Figure 9-15 EN 1823139 785 315329.Circuit- and IC Description PIN DESCRIPTION

27、AND CONFIGURATION PACKAGE PIN #PIN SYMBOLFUNCTION 1VCCPower supply input. 2PWRGDOpen collector output goes low when VFB is out of regulation. User must externally limit current into this pin to less than 20 mA. 3PGDELAYExternal capacitor programs PWRGD lowtohigh transition delay. 4COMPError amp outp

28、ut. PWM comparator reference input. A capacitor to LGND provides error amp compensation and Soft Start. Pulling pin 0.475 V locks gate outputs to a zero percent duty cycle state. 5GATE(H)Highside switch FET driver pin. Capable of delivering peak currents of 1.5 A. 6GATE(L)Lowside synchronous FET dri

29、ver pin. Capable of delivering peak currents of 1.5 A. 7VFBError amplifier and PWM comparator input. 8GNDPower supply return. IC7603 - ADV7322KST - Multi-Format 11-Bit HDTV Video Encoder BLOCK DIAGRAM CLKIN_A P_HSYNC P_VSYNC P_BLANK S_HSYNC S_VSYNC S_BLANK CLKIN_B HD PIXEL INPUT SD PIXEL INPUT LUMA

30、AND CHROMA FILTERS Y CB CR TEST PATTERN DNR GAMMA SYNC INSERTION PS 8? HDTV 2? RGB MATRIX SD 16? 2?OVER- SAMPLING DAC DAC DAC DAC DAC DAC FSC MODU- LATION CGMS WSS COLOR CONTROL DE- INTER- LEAVE Y CB CR DE- INTER- LEAVE TEST PATTERN Y COLOR CR COLOR CB COLOR TIMING GENERATOR TIMING GENERATOR CLOCK C

31、ONTROL AND PLL 4:2:2 TO 4:4:4 SHARPNESS AND ADAPTIVE FILTER CONTROL 05067-002 UV SSAF V U Figure 9-16 EN 1833139 785 315329.Circuit- and IC description PIN DESCRIPTION p Mnemonic Input/Output Function DGND G Digital Ground. AGND G Analog Ground. CLKIN_A I Pixel Clock Input for HD (74.25 MHz Only, PS

32、 Only (27 MHz), SD Only (27 MHz). CLKIN_B I Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV mode. This clock is only used in dual modes. COMP1, COMP2 O Compensation Pin for DACs. Connect 0.1 F capacitor from COMP pin

33、 to VAA. DAC A O CVBS/Green/Y/Y Analog Output. DAC B O Chroma/Blue/U/Pb Analog Output. DAC C O Luma/Red/V/Pr Analog Output. DAC D O In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Y/Green HD Analog Output. DAC E O In SD Only Mode: Luma/Blue/U Analog Output;

34、in HD Only Mode and Simultaneous HD/SD Mode: Pr/Red Analog Output. DAC F O In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Pb/Blue HD Analog Output. P_HSYNC I Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. P_VSYNC I

35、Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. P_BLANK I Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. S_BLANK I/O Video Blanking Control Signal for SD Only. S_HSYNC I/O Video Horizontal Sync Control Signal for SD Only. S_VS

36、YNC I/O Video Vertical Sync Control Signal for SD Only. Y7 to Y0 I SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan data. The LSB is set up on Pin Y0. C7 to C0 I Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb Blue/U data.

37、 The LSB is set up on Pin C0. S7 to S0 I SD or Progressive Scan/HDTV Input Port for Cr Red/V data in 4:4:4 input mode. LSB is set up on Pin S0. RESET I This input resets the on-chip timing generator and sets the ADV7322 into default register setting. RESET is an active low signal. RSET1, RSET2 I A 3

38、040 resistor must be connected from this pin to AGND and is used to control the amplitudes of the DAC outputs. SCLK I I2C Port Serial Interface Clock Input. SDA I/O I2C Port Serial Data Input/Output. ALSB I TTL Address Input. This signal sets up the LSB of the I2C address. When this pin is tied low,

39、 the I2C filter is activated, which reduces noise on the I2C interface. VDD_IO P Power Supply for Digital Inputs and Outputs. VDD P Digital Power Supply. VAA P Analog Power Supply. VREF I/O Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). EXT_LF I External Lo

40、op Filter for the Internal PLL. RTC_SCR_TR I Multifunctional Input. Real time control (RTC) input, timing reset input, subcarrier reset input. I2C I This input pin must be tied high (VDD_IO) for the ADV7322 to interface over the I2C port. GND_IO Digital Input/Output Ground. TEST0 to TEST5 I Not used

41、. Tie to DGND EN 1843139 785 315329.Circuit- and IC Description PIN CONFIGURATION 64 GND_IO 63 CLKIN_B 62 S7 61 S6 60 S5 59 S4 58 S3 57 DGND 56 VDD 55 S2 54 S1 53 S0 52 TEST5 51 TEST4 50 S_HSYNC 49 S_VSYNC 47RSET1 46VREF 45 COMP1 42 DAC C 43DAC B 44DAC A 48 S_BLANK 41VAA 40AGND 39DAC D 37 DAC F 36 C

42、OMP2 35 RSET2 34 EXT_LF 33 RESET 38 DAC E 2TEST0 3TEST1 4 Y0 7 Y3 6Y2 5Y1 1 VDD_IO 8Y4 9Y5 10VDD 12 Y6 13 Y7 14 TEST2 15 TEST3 16 C0 11 DGND 17 C1 18 C2 19 I2C 20 ALSB 21 SDA 22 SCLK 23 P_HSYNC 24 P_VSYNC 25 P_BLANK 26 C3 27 C4 28 C5 29 C6 30 C7 31 RTC_SCR_TR 32 CLKIN_A PIN 1 ADV7322 TOP VIEW (Not t

43、o Scale) 05067-019 Figure 9-17 EN 1853139 785 315329.Circuit- and IC description 9.6.3 HDMI Board IC7253 - ADV7320KSTZ - Multi-Format 216 MHz Video Encoder BLOCK DIAGRAM DE- INTER- LEAVE DE- INTER- LEAVE SHARPNESS & ADAPTIVE FILTER CONTROL TEST- PATTERN Y COLOR CR COLOR CB COLOR 4:2:2TO 4:4:4 TEST-

44、PATTERN DNR GAMMA COLOR- CONTROL SYNC INSER- TION UV SSAFRGB MATRIX PS 8X HDTV2X 2XOVER- SAMPLING FSC MODULA- TION CGMS WSS LUMA & CHROMA FILTERS SD 16X DAC DAC DAC TIMING GENERATOR Y CR CB Y CB CR U V HD PIXEL INPUT P_HSYNC P_VSYNC P_BLANK SD PIXEL INPUT CLOCK CONTROL & PLL CLKIN_A TIMING GENERATOR

45、 CLKIN_B S_HSYNC S_VSYNC S_BLANK DAC DAC DAC Figure 9-18 EN 1863139 785 315329.Circuit- and IC Description PIN DESCRIPTION Pin NameInput/OutputFunction D G N DGDigital Ground A G N DGAnalog Ground CLKIN_AIPixel Clock Input for HD (74.25MHz Only , PS Only (27MHz), SD Only (27MHz). CLKIN_BIPixel Clock

46、 Input. Requires a 27MHz reference clock for Progressive Scan Mode or a 74.25MHz (74.1758MHz) reference clock in HDTV mode. This Clock is only used in dual Modes. COMP1,2OCompensation Pin for DACs. Connect 0.1uF Capacitor from COMP pin to VAA. DACAOCVBS/ GREEN/ Y / Y analog output. DAC BOChroma/ BLU

47、E/ U / Pb analog output. DAC COLuma/ RED/ V / Pr analog output. DACDOIn SD onlyu mode: CVBS/Green/Y analog outptu, in HD only mode and simultaneous HD/SD mode: Y/Green HD analog output. DAC EOIn SD onlyu mode: Luma/Blue/U analog outptu, in HD only mode and simultaneous HD/SD mode: Pr/Red analog outp

48、ut. DAC FOIn SD onlyu mode: Chroma/Red/ V analog outptu, in HD only mode and simultaneous HD/SD mode: Pb/Blue HD analog output. P_HSYNCIVideo Horizontal Sync Control Signal for HD in simultaneous Sd/HD mode and HD mode only. P_VSYNCIVideo Vertical Sync Control Signal for HD in simultaneous SD/HD mod

49、e and HD mode only. P_BLANKIVideo Blanking Control signal for HD in simultaneous SD/HD mode and HD mode only. S_BLANKIVideo Blanking Control Signal for SD only. S_HSYNCIVideo Horizontal Sync Control Signal for SD only. S_VSYNCIVideo Vertical Sync Control Signal for SD only. Y9-0ISD or Progressive scan/ HDTV input port for Y data. Input port for interleaved Progressive Scan data. The LSB is set up on pin Y0. For 8-bit data input LSB is set up on Y2. C9-C0IProgre