Philips-DVDR-9000-H-Service-Manual(1) 电路图 维修手册.pdf

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1、Published by KC-TE 0547 AV Systems Printed in the Netherlands Subject to modifi cation EN 3139 785 31681 DVDR9000H/10/75/97HDD Video performance measured at Rear Cinch Audio Out: - S/N(Unweighted,5MHz-BW limitation, SC trap ON) : 52dB - Frequency response 0.1 to 4.8 MHz : +1/-5dB - Y/Chroma delay :

2、55ns 1.4.2.3 DVB-T- Audio Performance DVB-T RF antenna signal IN ; Audio performance measured at Rear Cinch Audio Out: - S/N(A-weighted, 22kHz-BW limited) : 88dB - Frequency response 20Hz to 20kHz : 1dB - THD + Noise (at 1 kHz) : 85dB - THD + noise (ratio) for 16Hz to 20kHz : 65dB - Channel Separati

3、on (at 1kHz) : 100dB 1.5 Analog Inputs / Outputs 1.5.1 SCART 1 (Connected to TV) Pin Signals: 1 Audio-out R 1.8V RMS 2 Audio-in R 3 Audio-out L 1.8V RMS 4 Audio GND 5 Blue / Chroma GND 6 Audio-in L 7 Blue-out 0.7Vpp 0.1V into 75 8 Function switch 4.5V / 9.5V / 12V = asp. Ratio 4:3 DVD 9 Green GND 10

4、 P50 control not use 11 Green out 0.7Vpp 0.1V into 75 12 NC 13 Red / Chroma GND 14 Fast switch GND 15 Red-out / 0.7Vpp 0.1V into 75 Chroma-out 300mVpp 3dB 16 Fast switch RGB / CVBS or Y out 1V / 10k Video - Cinch Input voltage : 1Vpp 3dB Input impedance : 75 Video - YC (Hosiden) According to IEC 933

5、-5 Superimposed DC-level on pin 4 (load = 100k) 3.5V is detected as 16:9 aspect ratio Input voltage Y : 1Vpp 3dB Input impedance Y : 75 Input voltage C : 300mVpp 3dB Input impedance C : 75 1.5.4 Out 1 Component Video Cinch Y/Pb/Pr according EIO-770-I-A, EIA-770-2 Audio - Cinch Output voltage : 2.2Vr

6、ms max. Output impedance : 10k 1.5.5 Out 2 Audio - Cinch Output voltage : 2Vrms max. Output impedance : 10k Video - Cinch Output voltage : 1Vpp 3dB Output impedance : 75 Video - YC (Hosiden) According to IEC 933-5 Superimposed DC-level on pin 4 (load 100k) 3.5V is detected as 16:9 aspect ratio Outpu

7、t voltage Y : 1Vpp 3dB Input impedance : 75 Output voltage C : 300mVpp 3dB Input impedance : 75 RadioFans.CN 收音机爱 好者资料库 EN 43139 785 316811. Technical Specifi cations and Connection Facilities 1.6 Digital Inputs / Outputs 1.6.1 Digital Output Digital Audio Coaxial / Optical LCM : according IEC 60958

8、 MPEG 1, MPEG 2, AC3 : according IEC 61937 DTS : according IEC 61937 + addendum 1.6.2 HDMI Output Type A connector (19 pins) 1.6.3 Digital Video Input (IEEE 1394) Implementation Standard according: IEEE Std 1394-1995 IEC61883 - Part1 IEC61883 - Part 2 SD-DVCR (02-01-1997) Specifi cation of consumer

9、use digital VCRs using 6.3mm magnetic tape dec.1994 Mechanical connection according to Annex of IEC 61883-1 1.6.4 G-Link (for IR-remote transmitting device) Output voltage : 5 0.5V (high level) 0.4 0.3V (low level) Output impedance : 150 1.7 Video Performance All outputs loaded with 75 SNR measureme

10、nts over full bandwidth without weighting. 1.7.1 SCART (RGB) SNR : 55dB on all output Bandwidth : 4.8MHz -3dB 1.8 Audio Performance 1.8.1 Cinch Output Rear Output voltage 2 channel mode : 2Vrms 2dB Channel unbalance (1kHz) : 100dB Crosstalk 16Hz-20kHz : 87dB Frequency response 20Hz-20kHz : 0.5dB Sig

11、nal to noise ratio (unweighted) : 85dB Dynamic range 1kHz : 83dB Distortion and noise 1kHz : 83dB Distortion and noise 16Hz-20kHz : 75dB Intermodulation distortion : 70dB Mute : 95dB 1.8.2 Scart Audio Output voltage 2 channel mode : 1.6Vrms 2dB Channel unbalance (1kHz) : 85dB Crosstalk 16Hz-20kHz :

12、70dB Frequency response 20Hz-20kHz : 0.5dB Signal to noise ratio (unweighted) : 80dB Dynamic range 1kHz : 75dB Distortion and noise 1kHz : 75dB Distortion and noise 16Hz-20kHz : 50dB Intermodulation distortion : 70dB Mute : 80dB 1.9 Dimensions and Weight Height of feet : 5.5mm Apparatus tray closed

13、: WxDxH:435x390 x89mm Apparatus tray open : WxDxH:435x525x89mm Weight without packaging : approx. 7.1 0.5kg Weight with packaging : approx. 8.5kg 1.10 Laser Output Power Wrong user input 40202 Address is not dividable by 4 Example DS: 402 0 xa1000010 0 xad112222 040200: Test OK Nucleus Name DS_SDRAM

14、_Read Nucleus Number 403 Description Read from a specific un-cached memory address Technical -Decode the user input and check the ranges -Read from the SDRAM and return this info to the user Execution Time Less than 1 second User Input The location from which the data must be read (SDRAM starts at a

15、ddress 0 xA0000000) Error Number Description 40300 Reading from the SDRAM succeeded 40301 Reading from the SDRAM failed; Wrong user input 40302 Address is not dividable by 4 Example DS: 403 0 xa1000010 040300: Value read = 0 xAD112222 Test OK Nucleus Name DS_SDRAM_DmaWriteRead Nucleus Number 404 Des

16、cription Write a pattern to the entire SDRAM using DMA and check the data Technical -Check if the Stack pointer is not in the write range -Clear a 64kb block and then fill it with a pattern -Initialise the DMA controller and write the data to the SDRAM -Then check if all the data was written correct

17、ly (except descriptor tables) -Repeat the process 4 times with 4 different patterns Execution Time 24 seconds User Input None. Error Number Description 40400 Writing to the SDRAM succeeded 40401 Stack area definition ERROR! 40402 DMA controller could not be initialised. 40403 Not all data was transf

18、erred correctly Example DS: 404 040400: Test OK EN 283139 785 31681Firmware Upgrading Wrong user input 50202 Address is not dividable by 4 Example DS: 502 0 xb8000000 050200: Value read = 0 x3C08A000 Test OK EN 293139 785 316815.Firmware Upgrading may be gated or used in a burst fashion. 27ISDATASer

19、ial Input, MSB first, containing two channels of 16, 18, 20, and 24 bits of twos complement data per channel. 28IDVDDDigital Power Supply Connect to digital 5 V supply. Table I. Serial Data Input Mode IDPM1 (Pin 20)IDPM0 (Pin 21)Serial Data Input Format 00Right-Justified 01I2S-Compatible 10Left-Just

20、ified 11DSP EN 2023139 785 316819.Circuit- and IC Description IC7007 - UDA 1361S - Analogue to Digital Converter BLOCK DIAGRAM, PIN DESCRIPTION AND CONFIGURATION handbook, full pagewidth UDA1361TS 1 VINL ADC DIGITAL INTERFACE DC-CANCELLATION FILTER DECIMATION FILTER CLOCK CONTROL 3 16 VINR ADC 13 DA

21、TAO 11 BCK 12 WS 6 SFOR 7 PWON 14 MSSEL 15 10 VSSD 9 VDDD VSSA 5 VRP 4 VRN 2 Vref 8 SYSCLK VDDA Figure 9-10 Block diagram. PINNING SYMBOLPINDESCRIPTION VINL1left channel input Vref2reference voltage VINR3right channel input VRN4negative reference voltage VRP5positive reference voltage SFOR6data form

22、at selection input PWON7power control input SYSCLK8system clock 256, 384, 512 or 768fs VDDD9digital supply voltage VSSD10digital ground BCK11bit clock input/output WS12word select input/output DA T A O13data output MSSEL14master/slave select VSSA15analog ground VDDA16analog supply voltage handbook,

23、halfpage UDA1361TS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VINL Vref VINR VRN VRP SFOR PWON SYSCLK VDDD VSSD BCK WS DATAO MSSEL VSSA VDDA Figure 9-11 Pin configuration. EN 2033139 785 316819.Circuit- and IC description IC7200 - NJM2584M - 2-Input 1-Output 3 Circuit Video Switch BLOCK DIAGRAM IN1A IN2

24、B IN3B 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 IN1B IN2A IN3A OUT1 OUT2 OUT3 NC CTL NC GND1 GND2 GND3 V+ BIAS CLAMP BIAS Figure 9-12 EN 2043139 785 316819.Circuit- and IC Description IC7201 - NJM2580M - 3-Channel Video Amplifi er BLOCK DIAGRAM 13 12 11 REF 1 2 3 4 7 5 6 14 8 10 9 V+ 1 GND1 GND2 GND3

25、VSAG VIN1 VIN2 VIN3 VOUT1 VOUT2 VOUT3 Power Save BIAS 6dB AMP 75 Driver BIAS 75 Driver 6dB AMP CLAMP 75 Driver 6dB AMP V+ 2 V+ 3 Figure 9-13 EN 2053139 785 316819.Circuit- and IC description IC7203 - NJM2267M - Dual Video 6dB Amplifi er BLOCK DIAGRAM Figure 9-14 EN 2063139 785 316819.Circuit- and IC

26、 Description IC7408 - STV6618D - Video Switch Matrix BLOCK DIAGRAM Sync Sep Bo. Clamp Y/CVBSIN_TUN Y/CVBSIN_TV Y/CVBSIN_AUX CVBSIN_ENC Bo. ClampG/YIN_AUX R/Pr/CIN_AUX B/PbIN_AUX Sync Sep Bo. ClampG/YIN_ENC R/Pr/CIN_ENC B/PbIN+ENC YIN_ENC CIN_TV CIN_ENC mute 0 dBY/CVBSOUT_REC Y/CVBSIN_TUN Y/CVBSIN_TV

27、 Y/CVBSIN_AUX CVBSIN_ENC YIN_ENC CIN_TV CIN_ENC G/YIN_ENC G/YIN_AUX R/Pr/CIN_AUX B/PbIN_AUX R/Pr/CIN_ENC B/PbIN_ENC STV6618D Recorder mute 6 dB Y/CVBSOUT_TV Scart1 mute 6 dB Y/CVBSOUT_AUX Scart2 mute 6 dB R/Pr/COUT_TV mute 6 dB G/YOUT_TV Scart1 Scart1 mute 6 dB B/PbOUT_TV Scart1 Y/CVBS_TUN Y/CVBS_TV

28、 Y/CVBS_AUX CVBSIN_ENC YIN_ENC CIN_TV CIN_ENC G/YIN_ENC G/YIN_AUX R/Pr/CIN_AUX B/PbIN_AUX R/Pr/CIN_ENC B/PbIN_ENC 0 dB FBOUT_TV SCL FBIN_AUX 0v 5v SDA C_GATE I2C bus Bo. Clamp Bo. Clamp Bo. Clamp Bo. Clamp Av. Clamp Av. Clamp Bot/sync/av. Bo/Sync Bot/sync Bot/sync/av. CVBSIN_TUN Y/CVBSIN_TV Y/CVBSIN

29、_AUX CVBSIN_ENC YIN_ENC mute 6 dB COUT_AUX Y/CVBSIN_AUX CVBSIN_ENC YIN_ENC CVBSIN_TUN Y/CVBSIN_TV CVBSIN_ENC YIN_ENC CIN_TV CIN_ENC CIN_ENC R/Pr/CIN_AUX R/Pr/CIN_ENC G/YIN_AUX G/YIN_ENC B/PbIN_AUX B/PbIN_ENC FBIN_AUX CIN_TUNAv. Clamp CIN_TUNCIN_TUN CIN_TUN DigOUT1 DigOUT2 DigOUT3 DigOUT4 DigOUT5 Dig

30、OUT6 Figure 9-15 EN 2073139 785 316819.Circuit- and IC description PIN DESCRIPTION AND CONFIGURATION gp Pin NumberSymbolDescription 1Y/CVBSIN_TUNY/CVBS Input from tuner 2digOUT3Digital output pin 3 3GND1ground, video inputs 4CVBSIN_ENCCVBS Input from Encoder 5DECVVideo decoupling capacitor 6CIN_ENCc

31、hroma Input from Encoder 7YIN_ENCY Input from Encoder 8Vcc+5 V Supply, video 9R/Pr/CIN_ENCRed or Pr or Chroma Input from Encoder 10G/YIN_ENCGreen or Y Input from Encoder 11B/PbIN_ENCBlue or Pb Input from Encoder 12GND2ground, video inputs 13B/PbIN_AUXBlue or Pb input from Auxiliary (scart2 or extern

32、al cinch) 14DigOUT4Digital output pin 4 15G/YIN_AUXGreen or Y input from Auxiliary (scart2 or external cinch) 16DigOUT5Digital output pin 5 17R/Pr/CIN_AUXRed or Pr or Chroma input from Auxiliary (scart2 or external cinch) 18DigOUT6Digital output pin 6 19Y/CVBSIN_AUXY/CVBS Input from Auxiliary (scart

33、2 or external cinch) 20VCCB_RECVideo Output recorder Buffer Supply Pin 21Y/CVBSOUT_RECY/CVBS Output to Recorder 22GNDB_RECground , recorder buffer 23COUT_AUXChroma Output to Auxiliary (scart2 or external cinch) 24VCCB1Video Output Buffer Supply Pin 25Y/CVBSOUT_AUXY/CVBS Output to Auxiliary(scart2 or

34、 external cinch) 26GNDBGround video buffer 27B/PbOUT_TVBlue or Pb output to TV (scart1 or external cinch) 28C_GATEexternal transistor command for bidirectinnal B/C scart I/O 29G/YOUT_TVGreen or Y output to TV (scart1 or external cinch) 30VCCB2Video Buffer 31R/Pr/COUT_TVRed or Pr or Chroma output to

35、TV (scart1 or external cinch) 32VCCB3Video Output Buffer Supply Pin 33Y/CVBSOUT_TVY/CVBS output to TV(scart1 or external cinch) 34FBOUT_TVFast Blanking Output to TV (scart1) 35FBIN_AUXFast blanking Input from auxiliary (scart2) 36VDD+5V digital supply 37SCLI2C Bus Clock 38SDAI2C Bus Data 39GNDDgroun

36、d digital 40CIN_TVChroma Input from TV (scart1 or external cinch) 41Y/CVBSIN_TVY/CVBS Input from TV (scart1 or external cinch) 42digOUT1Digital output pin 1 43CIN_TUNChroma Input from Tuner 44digOUT2Digital output pin 2 EN 2083139 785 316819.Circuit- and IC Description IC7212 - NJM2234M - 3-Input Vi

37、deo Switch BLOCK DIAGRAM Figure 9-16 IC7213 - NJM2235M - 3-Input Video Switch BLOCK DIAGRAM Figure 9-17 EN 2093139 785 316819.Circuit- and IC description IC - TMP87PM74ZFG - Microprocessor PIN CONFIGURATION Figure 9-18 EN 2103139 785 316819.Circuit- and IC Description 9.9.3 Digital Board IC7601 - NC

38、P1571D - Low voltage Synchronous Buck Controller BLOCK DIAGRAM + UVLO COMP + + + Fault Latch Set Dominant + 0.25 V Error Amp + R S Q PWM Latch Reset Dominant PWM COMP + OSC Art Ramp 80%, 200 kHz 0.525 V + 8.5 V/7.5 V + 0.980 V S R Q VCC GND VFB COMP GATE(H) GATE(L) PGDELAY PWRGD Non Overlap VCC + 0.

39、88 V/0.69 V + + 0.25 V S R Q PGDELAY Latch Set Dominant + + 3.3 V 12 A Figure 9-19 EN 2113139 785 316819.Circuit- and IC description PIN DESCRIPTION AND CONFIGURATION PACKAGE PIN #PIN SYMBOLFUNCTION 1VCCPower supply input. 2PWRGDOpen collector output goes low when VFB is out of regulation. User must

40、 externally limit current into this pin to less than 20 mA. 3PGDELAYExternal capacitor programs PWRGD lowtohigh transition delay. 4COMPError amp output. PWM comparator reference input. A capacitor to LGND provides error amp compensation and Soft Start. Pulling pin 0.475 V locks gate outputs to a zer

41、o percent duty cycle state. 5GATE(H)Highside switch FET driver pin. Capable of delivering peak currents of 1.5 A. 6GATE(L)Lowside synchronous FET driver pin. Capable of delivering peak currents of 1.5 A. 7VFBError amplifier and PWM comparator input. 8GNDPower supply return. IC7603 - ADV7322KST - Mul

42、ti-Format 11-Bit HDTV Video Encoder BLOCK DIAGRAM CLKIN_A P_HSYNC P_VSYNC P_BLANK S_HSYNC S_VSYNC S_BLANK CLKIN_B HD PIXEL INPUT SD PIXEL INPUT LUMA AND CHROMA FILTERS Y CB CR TEST PATTERN DNR GAMMA SYNC INSERTION PS 8? HDTV 2? RGB MATRIX SD 16? 2?OVER- SAMPLING DAC DAC DAC DAC DAC DAC FSC MODU- LAT

43、ION CGMS WSS COLOR CONTROL DE- INTER- LEAVE Y CB CR DE- INTER- LEAVE TEST PATTERN Y COLOR CR COLOR CB COLOR TIMING GENERATOR TIMING GENERATOR CLOCK CONTROL AND PLL 4:2:2 TO 4:4:4 SHARPNESS AND ADAPTIVE FILTER CONTROL 05067-002 UV SSAF V U Figure 9-20 EN 2123139 785 316819.Circuit- and IC Description

44、 PIN DESCRIPTION p Mnemonic Input/Output Function DGND G Digital Ground. AGND G Analog Ground. CLKIN_A I Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only (27 MHz). CLKIN_B I Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz (74.1758 MHz)

45、 reference clock in HDTV mode. This clock is only used in dual modes. COMP1, COMP2 O Compensation Pin for DACs. Connect 0.1 F capacitor from COMP pin to VAA. DAC A O CVBS/Green/Y/Y Analog Output. DAC B O Chroma/Blue/U/Pb Analog Output. DAC C O Luma/Red/V/Pr Analog Output. DAC D O In SD Only Mode: CV

46、BS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Y/Green HD Analog Output. DAC E O In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Pr/Red Analog Output. DAC F O In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneou

47、s HD/SD Mode: Pb/Blue HD Analog Output. P_HSYNC I Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. P_VSYNC I Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. P_BLANK I Video Blanking Control Signal for HD in Simultaneous S

48、D/HD Mode and HD Only Mode. S_BLANK I/O Video Blanking Control Signal for SD Only. S_HSYNC I/O Video Horizontal Sync Control Signal for SD Only. S_VSYNC I/O Video Vertical Sync Control Signal for SD Only. Y7 to Y0 I SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progre

49、ssive scan data. The LSB is set up on Pin Y0. C7 to C0 I Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb Blue/U data. The LSB is set up on Pin C0. S7 to S0 I SD or Progressive Scan/HDTV Input Port for Cr Red/V data in 4:4:4 input mode. LSB is set up on Pin S0. RESET I This input resets the on-chip timing generator and sets the ADV7322 into default register