Philips-DVDR-3355-Service-Manual(1) 电路图 维修手册.pdf

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1、Published by KC-TE 0530 AV Systems Printed in the Netherlands Subject to modifi cation EN 3139 785 30931 DVD-Video Recorder CLASS 1 LASER PRODUCT Contents Page 1 Technical Specifi cations and Connection Facilities 2 2 Safety Information, General Notes . To resume recording, press REC 0. To stop the

2、recording, press STOP 9. Wait until the message disappears from the display panel before you remove the disc. SUPER VIDEO Record Mode Picture Quality Maximum Recording Time per Disc 1 Hour Mode 2 Hour Mode 4 Hour Mode 6 Hour Mode High quality DVD quality-Standard Play VHS quality-Extended Play VHS q

3、uality-Super Long Play 1 hour 2 hours 4 hours 6 hours 3.Directions For Use EN 93139 785 3093x4.Mechanical Instructions 4. Mechanical Instructions 4.1 Dismantling and Assembly of the Set For item numbers please see the exploded view in Chapter 9. 4.1.1 Dismantling of the DVD Loader Tray Cover 1) Inse

4、rting a minus screw driver and push the lever in the direction as shown in Figure 4-1 to unlock the tray before sliding it out. Figure 4-1 2) Remove the Tray Cover as shown in Figure 4-2. Figure 4-2 4.1.2 Dismantling of the Front Panel Assembly 1) Remove the 3 screws 188 and release the 2 snap hooks

5、 on the side before removing the front assembly. 1 Figure 4-3 2) Remove the 5 screws 186 to remove the front plate 184 as shown in Figure 4-4. 2 2 Figure 4-4 EN 103139 785 3093x4.Mechanical Instructions 4.1.3 Dismantling of the Basic Engine 1) Remove the Cover Tray (See 4.1.1). 2) Remove the 4 screw

6、s 260 to free the Basic Engine. 3 3 Figure 4-5 3) Place the Basic Engine in the service position by fl ipping the basic engine to the vertical position Figure 4-6 4.1.4 Dismantling of the Digital Board 1) Remove the 4 screws 272 to loose the Digital Board as shown in Figure 4-7. 4 4 Figure 4-7 2) Se

7、rvice Position can be achieved by fl ipping the Digital board to the Vertical Position as shown in Figure 4-8. Figure 4-8 Note: The cable (just to transfer the service connection to the analog board) from socket 1101 can be removed and use for hyperterminal connection. EN 113139 785 3093x4.Mechanica

8、l Instructions 4.1.5 Dismantling of the Analog Board 1) Remove 5 screws 244 and 4 screws 252 and screw 230. 2) Remove 4 screws 270 and 3 screws 268. 3) Service Position can be achieved by fl ipping the analog board to the Vertical Position as shown in Figure 4-9. Figure 4-9 Note: Please cover the Li

9、ve Area during trouble-shooting. (Figure 4-10) Figure 4-10 Figure Live Area EN 123139 785 3093x5.Upgrade Software however, the SYSCLK output remains active. If the LPS input remains low for more than 26 s (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power disabled state in which the

10、 SYSCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state upon hardware reset. The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1, and is considered inactive if either the LPS input is inactive or the LCtrl reg

11、ister bit is cleared to 0. 48CMOSILLC request input. The LLC uses this input to initiate a service request to the TSB41AB1. Bus holder is built into this terminal. 16 17 18 CMOSIPower class programming inputs. On hardware reset, these inputs set the default value of the power class indicated during

12、self-ID. Programming is done by tying these terminals high or low. Refer to Table 9 for encoding. NAME DGND DVDD FILTER0 FILTER1 ISO LPS LREQ PC0 PC1 PC2 PD12CMOSIPower-down input. A high on this terminal turns off all internal circuitry except the cable-active monitor circuits, which control the CN

13、A output (64-terminal PAP package only). Asserting the PD input high also activates an internal pulldown on the RESET terminal to force a reset of the internal control logic. (PD is provided for legacy compatibility and is not recommended for power management in place of IEEE 1394a-2000 suspend/resu

14、me LPS and C/LKON features.) EN 643139 785 3093x8.Circuit- and IC Description TERMINAL TYPEI/ODESCRIPTION NAMEPHP NO. TYPEI/ODESCRIPTION 41SupplyPLL circuit ground terminals. These terminals should be tied together to the low-impedance circuit board ground plane. 40SupplyPLL circuit power terminals.

15、 A combination of high-frequency decoupling capacitors near each terminal is suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10 F filtering capacitors are also recommended. This supply terminal is separated from DVDD and AVDD inside the device to provide noise isolation. It should b

16、e tied at a low-impedance point on the circuit board. 33 34 BiasCurrent setting resistor terminals. These terminals are connected through an external resistor to set the internal operating currents and cable driver output currents. A resistance of 6.34 k 1.0% is required to meet the IEEE Std 1394-19

17、95 output voltage limits. 37CMOSILogic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to VDD is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in the Application Information section). The RES

18、ET terminal also incorporates an internal pulldown which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and may also be driven by an open-drain type driver. 23CMOSITest control input. This input is used in manufacturing test of the TSB41AB1. For norm

19、al use this terminal may be tied to GND through a 1-k pulldown resistor or it may be tied to GND directly. 24CMOSITest control input. This input is used in manufacturing test of the TSB41AB1. For normal use this terminal should be tied to GND. 1CMOSOSystem clock output. Provides a 49.152-MHz clock s

20、ignal, synchronized with data transfers, to the LLC. 22CMOSITest control input. This input is used in manufacturing test of the TSB41AB1. For normal use this terminal should be tied to VDD. 30CableI/OTwisted-pair cable A differential signal terminals. Board traces from the pair of positive and negat

21、ive differential signal terminals should be kept matched and as 29CableI/O positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. 28CableI/OTwisted-pair cable B differential signal terminals. Boar

22、d traces from the pair of positive and negative differential signal terminals should be kept matched and as 27CableI/O positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. 31CableI/OTwisted-pair

23、 bias output. This provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection. PLLGND PLLVDD R0 R1 RESET SE SM SYSCLK TESTM TPA+ TPA TPB+ TPB TPBIAS XI XO 42 43 C

24、rystalCrystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used (see crystal selection in the Application Information section). When an ex

25、ternal clock source is used, XI should be the input and XO should be left open, and the clock must be supplied before the device is powered on. EN 653139 785 3093x8.Circuit- and IC description IC7401 - TVP5146PFP - 4x10bit DigitalVideo Decoder with microvision BLOCK DIAGRAM Composite and S-Video Pro

26、cessor Y/C Separation 5-line Adaptive Comb Luma Processing Chroma Processing ADC1 ADC2 ADC3 ADC4 M U X Component Processor CVBS/Y C Y/G Pb/B Pr/R Gain/Offset Color Space Conversion C Y Output Formatter Y9:0 YCbCr VBI Data Slicer Copy Protection Detector C9:0 Host Interface Timing Processor with Sync

27、 Detector VI_1_A VI_1_B VI_1_C VI_2_A VI_2_B VI_2_C VI_3_A VI_3_B VI_3_C VI_4_A CVBS/ Y/G CVBS/ Pb/B/C CVBS/ Pr/R/C CVBS/Y CVBS/Y/G Analog Front End Sampling Clock GPIO FSS HS/CS VS/VBLK FID AVID XTAL1 XTAL2 DATACLK RESETB GLCO DR DG DB FSO PWDN SCL SDA YCbCr Figure 8-13 PIN CONFIGURATION 22 23 C_6/

28、GPIO/RED C_7/GPIO/GREEN C_8/GPIO/BLUE C_9/GPIO/FSO DGND DVDD Y_0 Y_1 Y_2 Y_3 Y_4 IOGND IOVDD Y_5 Y_6 Y_7 Y_8 Y_9 DGND DVDD 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VI_1_B VI_1_C CH1_A33GND CH1_A33VDD CH2_A33VDD CH2_A33GND VI_2_

29、A VI_2_B VI_2_C CH2_A18GND CH2_A18VDD A18VDD_REF A18GND_REF CH3_A18VDD CH3_A18GND VI_3_A VI_3_B VI_3_C CH3_A33GND CH3_A33VDD 25 26 27 28 PFP PACKAGE (TOP VIEW) 79 78 77 76 75807472 71 7073 29 30 31 32 33 69 68 21 67 66 65 64 34 35 36 37 38 39 40 63 62 61 VI_1_A CH1_A18GND CH1_A18VDD PLL_A18GND PLL_A

30、18VDD XTAL2 XTAL1 VS/VBLK/GPIO HS/CS/GPIO FID/GPIO C_0/GPIO C_1/GPIO DGND DVDD C_2/GPIO C_3/GPIO C_4/GPIO C_5/GPIO IOGND IOVDD CH4_A33VDD CH4_A33GND VI_4_A CH4_A18GND CH4_A18VDD AGND DGND SCL SDA INTREQ DVDD DGND PWDN RESETB FSS/GPIO AVID/GPIO GLCO/I2CA IOVDD IOGND DATACLK Figure 8-14 EN 663139 785

31、3093x8.Circuit- and IC Description PIN DESCRIPTION TERMINAL I/ODESCRIPTION NAMENUMBER I/ODESCRIPTION Analog Video VI_1_A VI_1_B VI_1_C VI_2_A VI_2_B VI_2_C VI_3_A VI_3_B VI_3_C VI_4_A 80 1 2 7 8 9 16 17 18 23 I VI_1_x: Analog video input for CVBS/Pb/B/C VI_2_x: Analog video input for CVBS/Y/G VI_3_x

32、: Analog video input for CVBS/Pr/R/C VI_4_A: Analog video input for CVBS/Y Up to 10 composite, 4 S-video, and 2 composite or 3 component video inputs (or a combination thereof) can be supported. The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 F. The possible input configurat

33、ions are listed in the input select register at I2C subaddress 00h (see Section 2.11.1). Clock Signals DATACLK40OLine-locked data output clock. XTAL174I External clock reference input. It may be connected to an external oscillator with a 1.8-V compatible clock signal or a 14.31818-MHz crystal oscill

34、ator. XTAL275OExternal clock reference output. Not connected if XTAL1 is driven by an external single-ended oscillator. Digital Video C9:0/ GPIO9:0 57, 58, 59, 60, 63, 64, 65, 66, 69, 70 O Digital video output of CbCr, C9 is MSB and C0 is LSB. Unused outputs can be left unconnected. Also, these term

35、inals can be programmable general-purpose I/O. For the 8-bit mode, the two LSBs are ignored. D_BLUE58IDigital BLUE input from overlay device D_GREEN59IDigital GREEN input from overlay device D_RED60IDigital RED input from overlay device FSO57IFast-switch overlay between digital RGB and any video Y9:

36、0 43, 44, 45, 46, 47, 50, 51, 52, 53, 54 O Digital video output of Y/YCbCr, Y9 is MSB and Y0 is LSB. For the 8-bit mode, the two LSBs are ignored. Unused outputs can be left unconnected. Miscellaneous Signals FSS/GPIO35I/O Fast-switch (blanking) input. Switching signal between the synchronous compon

37、ent video (YPbPr/RGB) and the composite video input. Programmable general-purpose I/O GLCO/I2CA37I/O Genlock control output (GLCO). Two Genlock data formats are available: TI format and real time control (RTC) format. During reset, this terminal is an input used to program the I2C address LSB. INTRE

38、Q30OInterrupt request PWDN33I Power down input: 1 = Power down 0 = Normal mode RESETB34IReset input, active low EN 673139 785 3093x8.Circuit- and IC description TERMINAL I/ODESCRIPTION NAMENUMBER I/ODESCRIPTION Host Interface SCL28II2C clock input SDA29I/OI2C data bus Power Supplies AGND26IAnalog gr

39、ound. Connect to analog ground. A18GND_REF13IAnalog 1.8-V return A18VDD_REF12IAnalog power for reference 1.8 V CH1_A18GND CH2_A18GND CH3_A18GND CH4_A18GND 79 10 15 24 IAnalog 1.8-V return CH1_A18VDD CH2_A18VDD CH3_A18VDD CH4_A18VDD 78 11 14 25 IAnalog power. Connect to 1.8 V. CH1_A33GND CH2_A33GND C

40、H3_A33GND CH4_A33GND 3 6 19 22 IAnalog 3.3-V return CH1_A33VDD CH2_A33VDD CH3_A33VDD CH4_A33VDD 4 5 20 21 IAnalog power. Connect to 3.3 V. DGND 27, 32, 42, 56, 68 IDigital return DVDD 31, 41, 55, 67 IDigital power. Connect to 1.8 V. IOGND39, 49, 62IDigital power return IOVDD38, 48, 61IDigital power.

41、 Connect to 3.3 V or less for reduced noise. PLL_A18GND77IAnalog power return PLL_A18VDD76IAnalog power. Connect to 1.8 V. Sync Signals HS/CS/GPIO72I/O Horizontal sync output or digital composite sync output Programmable general-purpose I/O VS/VBLK/GPIO73I/O Vertical sync output (for modes with dedi

42、cated VSYNC) or VBLK output Programmable general-purpose I/O FID/GPIO71I/O Odd/even field indicator output. This terminal needs a pulldown resistor. Programmable general-purpose I/O AVID/GPIO36I/O Active video indicator output Programmable general-purpose I/O EN 683139 785 3093x8.Circuit- and IC Des

43、cription IC7501 - TPS2041 - Power Distribution Switches BLOCK DIAGRAM OUT OC IN EN GND Current Limit Driver UVLO Charge Pump CS Thermal Sense Power Switch Current Sense Figure 8-15 PIN CONFIGURATION 1 2 3 4 8 7 6 5 GND IN IN EN OUT OUT OUT OC TPS2041 D OR P PACKAGE (TOP VIEW) Figure 8-16 EN 693139 7

44、85 3093x8.Circuit- and IC description PIN DESCRIPTION TERMINAL NO. I/ODESCRIPTION NAMED OR P I/ODESCRIPTION TPS2041TPS2051 EN4IEnable input. Logic low turns on power switch. EN4IEnable input. Logic high turns on power switch. GND11IGround IN2, 32, 3IInput voltage OC55OOver current. Logic output acti

45、ve low OUT6, 7, 86, 7, 8OPower-switch output IC7521 - L5972D - 2A Switch Step Down Switching Regulator PIN DESCRIPTION AND CONFIGURATION PIN CONNECTION PIN DESCRIPTION NPinFunction 1OUTRegulator Output. 2,3,6,7GNDGround. 4COMPE/A output for frequency compensation. 5FBFeedback input. Connecting direc

46、tly to this pin results in an output voltage of 1.23V. An external resistive divider is required for higher output voltages. 8VCCUnregulated DC input voltage. OUT GND GND COMP 1 3 2 4 VCC GND GND FB 8 7 6 5 D02IN1367 EN 703139 785 3093x8.Circuit- and IC Description IC7595 - NCP303 - Voltage Detector

47、 Series with Programmable Delay BLOCK DIAGRAM NCP303LSNxxT1 Open Drain Output Configuration Vref 2Input 3Gnd5CD RD 1Reset Output Figure 8-17 PIN DESCRIPTION AND CONFIGURATION PIN CONNECTIONS AND MARKING DIAGRAM 1 3N.C. Reset Output 2 Input Ground 4 CD5 xxxYW (Top View) xxx = 302 or 303 Y= Year W= Wo

48、rk Week Figure 8-18 EN 713139 785 3093x P003 P001 P002 3139 249 2798 2005-03-02 Exploded View of the Set Figure 9-1 9.Exploded View & Spare Parts List EN 723139 785 3093x9.Exploded View & Spare Parts List Spare Parts List 0002 3139 247 11131 MODULE DRIVE D4.3 0164 3103 601 20231 SPRING GROUND 0168 3

49、103 601 20212 SPRING I-LINK 0196 3139 241 22761 COVER TOP DVDR3305 0228 3139 241 22791 PLATE REAR EU DVDR3305 0288 4822 532 60948 BUSH 0333 2422 549 00607 REMOTE CONTR DVDR3365/EU B 0333 2422 549 00611 REMOTE CONTR DVDR3355/DVDR3305 0336 4822 321 11499 MAINSCORD /02, /19, /51 only 0336 2422 070 98236 MAINSCORD UK 5A 1M8 VH BK B /05 only 0342 2422 076 00532 CBLE SCART 1M5 SCART 21P BK B 0345 4822 320 50377 CONNECT. CABLE PAL 0901 3143 027 62231 FRONT ASSY DVDR3365 /02, /19, /51 only 0901 3143 027 62261 FRONT ASSY DVDR3365 /05 only 0901 3143